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llvm-mirror/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

47 lines
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# RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips %s -start-after=xray-instrumentation -o - -show-mc-encoding | FileCheck %s
# Test that the 'sll $zero, $zero, 0' is correctly recognized as a real
# instruction rather than some unimplemented opcode for the purposes of
# encoding an instruction.
# CHECK-LABEL: a:
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK: jrc $ra # encoding: [0x45,0xbf]
---
name: a
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: false
registers:
liveins:
- { reg: '$a0', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
$zero = SLL_MMR6 killed $zero, 0
JRC16_MM undef $ra, implicit $v0
...