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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
47 lines
1.2 KiB
YAML
47 lines
1.2 KiB
YAML
# RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips %s -start-after=xray-instrumentation -o - -show-mc-encoding | FileCheck %s
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# Test that the 'sll $zero, $zero, 0' is correctly recognized as a real
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# instruction rather than some unimplemented opcode for the purposes of
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# encoding an instruction.
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# CHECK-LABEL: a:
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# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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# CHECK: jrc $ra # encoding: [0x45,0xbf]
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---
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name: a
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: false
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registers:
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liveins:
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- { reg: '$a0', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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$zero = SLL_MMR6 killed $zero, 0
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JRC16_MM undef $ra, implicit $v0
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...
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