Zakk Chen 03a2d56fa7 [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. ... Fix the unexpected of using op1's element type as shift amount type. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D98501		2021-03-17 10:47:49 -07:00
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GlobalISel
intrinsics
rvv	[RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.	2021-03-17 10:47:49 -07:00
add-before-shl.ll
add-imm.ll
addc-adde-sube-subc.ll
addcarry.ll
addimm-mulimm.ll
addrspacecast.ll
align.ll
alloca.ll
alu8.ll
alu16.ll
alu32.ll
alu64.ll
analyze-branch.ll
arith-with-overflow.ll
atomic-cmpxchg-flag.ll
atomic-cmpxchg.ll
atomic-fence.ll
atomic-load-store.ll
atomic-rmw.ll
attributes.ll
blockaddress.ll
branch-relaxation.ll
branch.ll	[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)	2021-03-15 11:32:43 -07:00
bswap-ctlz-cttz-ctpop.ll
byval.ll
callee-saved-fpr32s.ll
callee-saved-fpr64s.ll
callee-saved-gprs.ll
calling-conv-ilp32-ilp32f-common.ll
calling-conv-ilp32-ilp32f-ilp32d-common.ll
calling-conv-ilp32.ll
calling-conv-ilp32d.ll
calling-conv-ilp32f-ilp32d-common.ll
calling-conv-lp64-lp64f-common.ll
calling-conv-lp64-lp64f-lp64d-common.ll
calling-conv-lp64.ll
calling-conv-rv32f-ilp32.ll
calling-conv-sext-zext.ll
calls.ll
cmp-bool.ll
codemodel-lowering.ll
compress-float.ll
compress-inline-asm.ll
compress.ll
copy-frameindex.mir
copysign-casts.ll
disable-tail-calls.ll
disjoint.ll
div.ll
double-arith.ll
double-bitmanip-dagcombines.ll
double-br-fcmp.ll
double-calling-conv.ll
double-convert.ll
double-fcmp.ll
double-frem.ll
double-imm.ll
double-intrinsics.ll
double-isnan.ll
double-mem.ll
double-previous-failure.ll
double-select-fcmp.ll
double-stack-spill-restore.ll
dwarf-eh.ll
exception-pointer-register.ll
fastcc-float.ll
fastcc-int.ll
fixups-diff.ll
fixups-relax-diff.ll
float-arith.ll
float-bit-preserving-dagcombines.ll
float-bitmanip-dagcombines.ll
float-br-fcmp.ll
float-convert.ll
float-fcmp.ll
float-frem.ll
float-imm.ll
float-intrinsics.ll
float-isnan.ll
float-mem.ll
float-select-fcmp.ll
flt-rounds.ll
fold-addi-loadstore.ll
fp16-promote.ll
fp128.ll
fp-imm.ll
frame-info.ll
frame.ll
frameaddr-returnaddr.ll
get-register-invalid.ll
get-register-noreserve.ll
get-register-reserve.ll
get-setcc-result-type.ll
ghccc-rv32.ll
ghccc-rv64.ll
half-arith.ll
half-bitmanip-dagcombines.ll
half-br-fcmp.ll
half-convert.ll
half-fcmp.ll
half-imm.ll
half-intrinsics.ll
half-isnan.ll
half-mem.ll
half-select-fcmp.ll
hoist-global-addr-base.ll	[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)	2021-03-15 11:32:43 -07:00
i32-icmp.ll
imm-cse.ll
imm.ll
indirectbr.ll
init-array.ll
inline-asm-abi-names.ll
inline-asm-clobbers.ll
inline-asm-d-abi-names.ll
inline-asm-d-constraint-f.ll
inline-asm-f-abi-names.ll
inline-asm-f-constraint-f.ll
inline-asm-i-constraint-i1.ll
inline-asm-invalid.ll
inline-asm.ll
interrupt-attr-args-error.ll
interrupt-attr-callee.ll
interrupt-attr-invalid.ll
interrupt-attr-nocall.ll
interrupt-attr-ret-error.ll
interrupt-attr.ll
jumptable.ll
large-stack.ll
legalize-fneg.ll
lit.local.cfg
lsr-legaladdimm.ll
machineoutliner.mir
mattr-invalid-combination.ll
mem64.ll
mem.ll
mir-target-flags.ll
module-target-abi2.ll
module-target-abi.ll
mul.ll
musttail-call.ll
neg-abs.ll
nomerge.ll
option-nopic.ll
option-norelax.ll
option-norvc.ll
option-pic.ll
option-relax.ll
option-rvc.ll
out-of-reach-emergency-slot.mir
patchable-function-entry.ll	[RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'	2021-03-16 10:02:35 -07:00
pic-models.ll
pr40333.ll
prefetch.ll
readcyclecounter.ll
rem.ll
remat.ll
reserved-reg-errors.ll
reserved-regs.ll
rotl-rotr.ll
rv32e.ll
rv32i-rv64i-float-double.ll
rv32i-rv64i-half.ll
rv32Zba.ll
rv32Zbb.ll
rv32Zbbp.ll
rv32Zbp.ll
rv32Zbs.ll
rv32Zbt.ll
rv64-large-stack.ll
rv64d-double-convert.ll
rv64f-float-convert.ll
rv64f-half-convert.ll
rv64i-complex-float.ll
rv64i-demanded-bits.ll
rv64i-double-softfloat.ll
rv64i-exhaustive-w-insts.ll
rv64i-single-softfloat.ll
rv64i-tricky-shifts.ll
rv64i-w-insts-legalization.ll
rv64m-exhaustive-w-insts.ll
rv64m-w-insts-legalization.ll
rv64Zba.ll
rv64Zbb.ll
rv64Zbbp.ll
rv64Zbp.ll
rv64Zbs.ll
rv64Zbt.ll
sadd_sat_plus.ll	[RISCV] Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) -> (select_cc X, Y, eq/ne, trueV, falseV)	2021-03-07 09:29:55 -08:00
sadd_sat.ll	[RISCV] Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) -> (select_cc X, Y, eq/ne, trueV, falseV)	2021-03-07 09:29:55 -08:00
saverestore.ll
scalable-vector-struct.ll
sdata-limit-0.ll
sdata-limit-4.ll
sdata-limit-8.ll
sdata-local-sym.ll
select-and.ll
select-bare.ll
select-cc.ll	[RISCV] Teach normaliseSetCC to canonicalize X > -1 to X >= 0 and X < 1 to 0 >= X.	2021-03-12 11:50:10 -08:00
select-const.ll
select-optimize-multiple.ll
select-optimize-multiple.mir
select-or.ll
setcc-logic.ll
sext-zext-trunc.ll
shadowcallstack.ll
shift-masked-shamt.ll
shifts.ll
shrinkwrap.ll
spill-fpr-scalar.ll
split-offsets.ll
split-sp-adjust.ll
srem-lkk.ll
srem-seteq-illegal-types.ll	Test cases for rem-seteq fold with illegal types	2021-03-12 16:28:04 +02:00
srem-vector-lkk.ll
ssub_sat_plus.ll	[RISCV] Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) -> (select_cc X, Y, eq/ne, trueV, falseV)	2021-03-07 09:29:55 -08:00
ssub_sat.ll	[RISCV] Fold (select_cc (xor X, Y), 0, eq/ne, trueV, falseV) -> (select_cc X, Y, eq/ne, trueV, falseV)	2021-03-07 09:29:55 -08:00
stack-realignment-with-variable-sized-objects.ll
stack-realignment.ll
stack-store-check.ll
subtarget-features-std-ext.ll
tail-calls.ll
target-abi-invalid.ll
target-abi-valid.ll
thread-pointer.ll
tls-models.ll
uadd_sat_plus.ll	[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.	2021-03-16 07:44:06 -07:00
uadd_sat.ll	[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.	2021-03-16 07:44:06 -07:00
umulo-128-legalisation-lowering.ll
urem-lkk.ll
urem-seteq-illegal-types.ll	Test cases for rem-seteq fold with illegal types	2021-03-12 16:28:04 +02:00
urem-vector-lkk.ll
usub_sat_plus.ll	[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.	2021-03-16 07:44:06 -07:00
usub_sat.ll	[RISCV] Improve i32 UADDSAT/USUBSAT on RV64.	2021-03-16 07:44:06 -07:00
vararg.ll
vec3-setcc-crash.ll
verify-instr.mir
wide-mem.ll
xaluo.ll	[RISCV] Add RISCVISD::BR_CC similar to RISCVISD::SELECT_CC.	2021-03-15 11:54:01 -07:00
zext-with-load-is-free.ll
zfh-imm.ll