Krzysztof Parzyszek 36b88f31f1 [Hexagon] Improve stack address base reuse for HVX spills ... The offset in HVX loads/stores is only 4 bits long, so often an extra register is needed to hold the address. Minimize the number of such registers by "standardizing" the base addresses and reusing preexisting base registers when replacing frame indices.		2021-03-17 21:22:56 -05:00
..
AArch64	[GlobalISel] Don't DCE LIFETIME_START/LIFETIME_END markers.	2021-03-17 18:02:08 -07:00
AMDGPU	[DAG] TargetLowering::isBinOp() - add ISD::SSUBSAT/USUBSAT	2021-03-17 14:51:00 +00:00
ARC
ARM	[ARM] Use lrdsb for more thumb1 loads.	2021-03-17 15:29:02 +00:00
AVR
BPF
Generic
Hexagon	[Hexagon] Improve stack address base reuse for HVX spills	2021-03-17 21:22:56 -05:00
Inputs
Lanai
M68k	[M68k] Fixed incorrect extract-section command substitution	2021-03-16 13:37:50 -07:00
Mips
MIR	[AMDGPU] Use single cache policy operand	2021-03-15 13:00:59 -07:00
MSP430
NVPTX	[NVPTX] CUDA does provide malloc/free since compute capability 2.X	2021-03-15 22:45:56 -05:00
PowerPC	[NFC] [XCOFF] Update PowerPC readobj test case with expression	2021-03-17 16:02:50 +08:00
RISCV	[RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.	2021-03-17 10:47:49 -07:00
SPARC
SystemZ
Thumb	[ARM] Use lrdsb for more thumb1 loads.	2021-03-17 15:29:02 +00:00
Thumb2
VE
WebAssembly
WinCFGuard
WinEH
X86	[X86][SSE] Add SSE2/SSE42 test coverage to urem combine tests	2021-03-17 19:58:03 +00:00
XCore