Jessica Clarke d84def18b6 [RISCV] Duplicate pseudo expansion comment to RISCVMCCodeEmitter ... Follow-on from D77443. Although we're not fixing any of these pseudo-instructions, the potential for them to be out of sync still exists.		2020-07-15 10:52:42 +01:00
..
AsmParser	[RISCV] Silence unused variable warning in Release builds. NFC.	2020-06-27 23:24:28 +02:00
Disassembler	[RISCV] Assemble/Disassemble v-ext instructions.	2020-06-28 00:54:07 +08:00
MCTargetDesc	[RISCV] Duplicate pseudo expansion comment to RISCVMCCodeEmitter	2020-07-15 10:52:42 +01:00
TargetInfo
Utils	[RISCV] Assemble/Disassemble v-ext instructions.	2020-06-28 00:54:07 +08:00
CMakeLists.txt	[RISCV] Split the pseudo instruction splitting pass	2020-06-29 14:35:57 +01:00
LLVMBuild.txt
RISCV.h	[RISCV] Split the pseudo instruction splitting pass	2020-06-29 14:35:57 +01:00
RISCV.td	[RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive	2020-07-09 23:07:39 -07:00
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVExpandAtomicPseudoInsts.cpp	[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos	2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp	[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos	2020-07-15 10:50:55 +01:00
RISCVFrameLowering.cpp	[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align	2020-07-01 07:28:11 +00:00
RISCVFrameLowering.h
RISCVInstrFormats.td	[RISCV] Assemble/Disassemble v-ext instructions.	2020-06-28 00:54:07 +08:00
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td	[RISCV] Assemble/Disassemble v-ext instructions.	2020-06-28 00:54:07 +08:00
RISCVInstrInfo.cpp	[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos	2020-07-15 10:50:55 +01:00
RISCVInstrInfo.h	[RISCV] Assemble/Disassemble v-ext instructions.	2020-06-28 00:54:07 +08:00
RISCVInstrInfo.td	[RISCV] Assemble/Disassemble v-ext instructions.	2020-06-28 00:54:07 +08:00
RISCVInstrInfoA.td	RISCV: Avoid GlobalISel build break in a future patch	2020-07-13 14:01:57 -04:00
RISCVInstrInfoB.td
RISCVInstrInfoC.td
RISCVInstrInfoD.td
RISCVInstrInfoF.td
RISCVInstrInfoM.td
RISCVInstrInfoV.td	[RISCV] Assemble/Disassemble v-ext instructions.	2020-06-28 00:54:07 +08:00
RISCVInstructionSelector.cpp	RISCV: Avoid GlobalISel build break in a future patch	2020-07-13 14:01:57 -04:00
RISCVISelDAGToDAG.cpp	[RISCV] optimize addition with a pair of (addi imm)	2020-07-07 18:57:28 -07:00
RISCVISelDAGToDAG.h
RISCVISelLowering.cpp	[RISCV] Optimize multiplication by constant	2020-07-07 18:50:24 -07:00
RISCVISelLowering.h	[RISCV] Optimize multiplication by constant	2020-07-07 18:50:24 -07:00
RISCVLegalizerInfo.cpp
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h	[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align	2020-07-01 07:28:11 +00:00
RISCVMCInstLower.cpp	Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"	2020-07-14 11:15:01 +01:00
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp	RISCV: Don't store function in RISCVMachineFunctionInfo	2020-06-30 16:08:51 -04:00
RISCVRegisterInfo.h
RISCVRegisterInfo.td	[RISCV] Assemble/Disassemble v-ext instructions.	2020-06-28 00:54:07 +08:00
RISCVSchedRocket32.td	[RISCV] Assemble/Disassemble v-ext instructions.	2020-06-28 00:54:07 +08:00
RISCVSchedRocket64.td	[RISCV] Assemble/Disassemble v-ext instructions.	2020-06-28 00:54:07 +08:00
RISCVSchedule.td
RISCVSubtarget.cpp
RISCVSubtarget.h	[RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive	2020-07-09 23:07:39 -07:00
RISCVSystemOperands.td	[RISCV] Add mcountinhibit CSR	2020-07-01 08:27:00 -07:00
RISCVTargetMachine.cpp	Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"	2020-07-14 11:15:01 +01:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp
RISCVTargetTransformInfo.h