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b15b82c418
With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations. This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware). While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions. Differential Revision: https://reviews.llvm.org/D24343 llvm-svn: 281852
72 lines
2.5 KiB
LLVM
72 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32-AVX
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX
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;PR29079
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define <4 x float> @mask_ucvt_4i32_4f32(<4 x i32> %a) {
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; X32-SSE-LABEL: mask_ucvt_4i32_4f32:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: andps {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
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; X32-SSE-NEXT: retl
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;
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; X32-AVX-LABEL: mask_ucvt_4i32_4f32:
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; X32-AVX: # BB#0:
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; X32-AVX-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0
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; X32-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
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; X32-AVX-NEXT: retl
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;
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; X64-SSE-LABEL: mask_ucvt_4i32_4f32:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; X64-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
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; X64-SSE-NEXT: retq
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;
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; X64-AVX-LABEL: mask_ucvt_4i32_4f32:
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; X64-AVX: # BB#0:
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; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; X64-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
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; X64-AVX-NEXT: retq
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%and = and <4 x i32> %a, <i32 127, i32 255, i32 4095, i32 65595>
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%cvt = uitofp <4 x i32> %and to <4 x float>
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ret <4 x float> %cvt
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}
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define <4 x double> @mask_ucvt_4i32_4f64(<4 x i32> %a) {
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; X32-SSE-LABEL: mask_ucvt_4i32_4f64:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: cvtdq2pd %xmm0, %xmm2
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; X32-SSE-NEXT: cvtdq2pd %xmm0, %xmm1
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; X32-SSE-NEXT: movaps %xmm2, %xmm0
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; X32-SSE-NEXT: retl
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;
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; X32-AVX-LABEL: mask_ucvt_4i32_4f64:
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; X32-AVX: # BB#0:
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; X32-AVX-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0
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; X32-AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
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; X32-AVX-NEXT: retl
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;
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; X64-SSE-LABEL: mask_ucvt_4i32_4f64:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm2
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; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm1
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; X64-SSE-NEXT: movaps %xmm2, %xmm0
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; X64-SSE-NEXT: retq
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;
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; X64-AVX-LABEL: mask_ucvt_4i32_4f64:
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; X64-AVX: # BB#0:
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; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; X64-AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
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; X64-AVX-NEXT: retq
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%and = and <4 x i32> %a, <i32 127, i32 255, i32 4095, i32 65595>
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%cvt = uitofp <4 x i32> %and to <4 x double>
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ret <4 x double> %cvt
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}
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