Chandler Carruth 728acc9bd9 Flip the new block-placement pass to be on by default. ... This is mostly to test the waters. I'd like to get results from FNT build bots and other bots running on non-x86 platforms. This feature has been pretty heavily tested over the last few months by me, and it fixes several of the execution time regressions caused by the inlining work by preventing inlining decisions from radically impacting block layout. I've seen very large improvements in yacr2 and ackermann benchmarks, along with the expected noise across all of the benchmark suite whenever code layout changes. I've analyzed all of the regressions and fixed them, or found them to be impossible to fix. See my email to llvmdev for more details. I'd like for this to be in 3.1 as it complements the inliner changes, but if any failures are showing up or anyone has concerns, it is just a flag flip and so can be easily turned off. I'm switching it on tonight to try and get at least one run through various folks' performance suites in case SPEC or something else has serious issues with it. I'll watch bots and revert if anything shows up. llvm-svn: 154816		2012-04-16 13:49:17 +00:00
..
useful-harnesses
2009-01-01-BrCond.ll	Flip the new block-placement pass to be on by default.	2012-04-16 13:49:17 +00:00
2010-04-07-DbgValueOtherTargets.ll	If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.	2010-12-06 22:39:26 +00:00
and_ops.ll	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
arg_ret.ll	Fix memory access lowering on SPU, adding	2010-11-12 10:14:03 +00:00
bigstack.ll	Have SPU handle halfvec stores aligned by 8 bytes.	2010-08-09 16:33:00 +00:00
bss.ll	Be nice to Xcore and the XMOS assembler and avoid quoting section names	2011-03-04 20:03:14 +00:00
call.ll	Remove histogram tests.	2011-11-12 22:39:40 +00:00
crash.ll	teach cellspu how to return i8 and i16 from calls,	2010-04-20 05:36:09 +00:00
ctpop.ll
div_ops.ll	Division by pow-of-2 is not cheap on SPU, do it with	2010-11-23 13:27:59 +00:00
dp_farith.ll	Delete useless trailing semicolons.	2010-01-05 17:55:26 +00:00
eqv.ll	manually upgrade a bunch of tests to modern syntax, and remove some that	2011-06-17 03:14:27 +00:00
extract_elt.ll
fcmp32.ll	Allow for 'fcmp ogt' in SPU.	2010-11-24 11:42:17 +00:00
fcmp64.ll
fdiv.ll
fneg-fabs.ll
i8ops.ll
i64ops.ll
icmp8.ll
icmp16.ll
icmp32.ll
icmp64.ll
immed16.ll
immed32.ll	Don't feed 19 bit immediates to ILA.	2010-12-17 09:36:09 +00:00
immed64.ll
int2fp.ll
intrinsics_branch.ll
intrinsics_float.ll
intrinsics_logical.ll
jumptable.ll	Mark 'branch indirect' instruction as an indirect branch.	2011-10-13 11:40:03 +00:00
lit.local.cfg	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
loads.ll	Allow load from constant on SPU.	2011-03-04 12:00:11 +00:00
mul_ops.ll	Teach dag combine to fold the following transformation more aggressively:	2010-01-06 19:38:29 +00:00
mul-with-overflow.ll	manually upgrade a bunch of tests to modern syntax, and remove some that	2011-06-17 03:14:27 +00:00
nand.ll	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
or_ops.ll	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
private.ll	make the asmparser reject function and type redefinitions. 'Merging' hasn't been	2011-06-17 07:06:44 +00:00
rotate_ops.ll	1. Remove the part of r153848 which optimizes shuffle-of-shuffle into a new	2012-04-07 21:19:08 +00:00
select_bits.ll	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
sext128.ll	Allow sign-extending of i8 and i16 to i128 on SPU.	2011-01-20 15:49:06 +00:00
shift_ops.ll	Enable element promotion type legalization by deafault.	2011-10-16 20:31:33 +00:00
shuffles.ll	Enable element promotion type legalization by deafault.	2011-10-16 20:31:33 +00:00
sp_farith.ll
stores.ll	Allow load from constant on SPU.	2011-03-04 12:00:11 +00:00
storestruct.ll	"on the rare occasion the SPU BE produces illegal assembly - it tries to emit an add instruction of the form 'a reg, reg, imm'."	2010-05-04 17:58:46 +00:00
struct_1.ll	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
sub_ops.ll	Fix encoding of 'sf' and 'sfh' instructions.	2010-05-10 08:13:49 +00:00
trunc.ll
v2f32.ll	don't test for codegen of 'store undef'	2011-04-09 02:31:26 +00:00
v2i32.ll	Enable element promotion type legalization by deafault.	2011-10-16 20:31:33 +00:00
vec_const.ll
vecinsert.ll	Fix SPU to cope with vector insertelement to an undef position.	2010-06-09 09:58:17 +00:00