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https://github.com/RPCS3/llvm-mirror.git
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bf9d9a1180
Previously this would default to 256, not the maximum supported size of 1024. Using a maximum lower than the hardware maximum requires language runtimes to enforce this limit for correctness, which no language has correctly done. Switch the default to the conservatively correct maximum, and force frontends to opt-in to the more optimal 256 default maximum. I don't really understand why the changes in occupancy-levels.ll increased the computed occupancy, which I expected to decrease. I'm not sure if these tests should be forcing the old maximum.
304 lines
13 KiB
LLVM
304 lines
13 KiB
LLVM
; RUN: llc -march=r600 -mcpu=redwood -disable-promote-alloca-to-vector < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600-VECT -check-prefix=FUNC
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; RUN: opt -S -mtriple=r600-unknown-unknown -mcpu=redwood -amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck -check-prefix=OPT %s
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target datalayout = "A5"
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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; FUNC-LABEL: {{^}}mova_same_clause:
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; R600: LDS_WRITE
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; R600: LDS_WRITE
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; R600: LDS_READ
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; R600: LDS_READ
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; OPT: call i32 @llvm.r600.read.local.size.y(), !range !0
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; OPT: call i32 @llvm.r600.read.local.size.z(), !range !0
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; OPT: call i32 @llvm.r600.read.tidig.x(), !range !1
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; OPT: call i32 @llvm.r600.read.tidig.y(), !range !1
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; OPT: call i32 @llvm.r600.read.tidig.z(), !range !1
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define amdgpu_kernel void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 {
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entry:
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%stack = alloca [5 x i32], align 4, addrspace(5)
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%0 = load i32, i32 addrspace(1)* %in, align 4
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%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %0
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store i32 4, i32 addrspace(5)* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
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%1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %1
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store i32 5, i32 addrspace(5)* %arrayidx3, align 4
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%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
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%2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
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store i32 %2, i32 addrspace(1)* %out, align 4
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%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
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%3 = load i32, i32 addrspace(5)* %arrayidx12
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%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
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store i32 %3, i32 addrspace(1)* %arrayidx13
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ret void
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}
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; This test checks that the stack offset is calculated correctly for structs.
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; All register loads/stores should be optimized away, so there shouldn't be
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; any MOVA instructions.
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;
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; XXX: This generated code has unnecessary MOVs, we should be able to optimize
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; this.
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; FUNC-LABEL: {{^}}multiple_structs:
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; R600-NOT: MOVA_INT
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%struct.point = type { i32, i32 }
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define amdgpu_kernel void @multiple_structs(i32 addrspace(1)* %out) #0 {
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entry:
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%a = alloca %struct.point, addrspace(5)
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%b = alloca %struct.point, addrspace(5)
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%a.x.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %a, i32 0, i32 0
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%a.y.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %a, i32 0, i32 1
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%b.x.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %b, i32 0, i32 0
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%b.y.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %b, i32 0, i32 1
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store i32 0, i32 addrspace(5)* %a.x.ptr
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store i32 1, i32 addrspace(5)* %a.y.ptr
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store i32 2, i32 addrspace(5)* %b.x.ptr
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store i32 3, i32 addrspace(5)* %b.y.ptr
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%a.indirect.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %a, i32 0, i32 0
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%b.indirect.ptr = getelementptr inbounds %struct.point, %struct.point addrspace(5)* %b, i32 0, i32 0
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%a.indirect = load i32, i32 addrspace(5)* %a.indirect.ptr
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%b.indirect = load i32, i32 addrspace(5)* %b.indirect.ptr
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%0 = add i32 %a.indirect, %b.indirect
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; Test direct access of a private array inside a loop. The private array
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; loads and stores should be lowered to copies, so there shouldn't be any
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; MOVA instructions.
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; FUNC-LABEL: {{^}}direct_loop:
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; R600-NOT: MOVA_INT
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define amdgpu_kernel void @direct_loop(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
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entry:
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%prv_array_const = alloca [2 x i32], addrspace(5)
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%prv_array = alloca [2 x i32], addrspace(5)
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%a = load i32, i32 addrspace(1)* %in
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%b_src_ptr = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
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%b = load i32, i32 addrspace(1)* %b_src_ptr
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%a_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array_const, i32 0, i32 0
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store i32 %a, i32 addrspace(5)* %a_dst_ptr
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%b_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array_const, i32 0, i32 1
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store i32 %b, i32 addrspace(5)* %b_dst_ptr
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br label %for.body
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for.body:
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%inc = phi i32 [0, %entry], [%count, %for.body]
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%x_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array_const, i32 0, i32 0
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%x = load i32, i32 addrspace(5)* %x_ptr
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%y_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array, i32 0, i32 0
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%y = load i32, i32 addrspace(5)* %y_ptr
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%xy = add i32 %x, %y
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store i32 %xy, i32 addrspace(5)* %y_ptr
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%count = add i32 %inc, 1
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%done = icmp eq i32 %count, 4095
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br i1 %done, label %for.end, label %for.body
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for.end:
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%value_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array, i32 0, i32 0
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%value = load i32, i32 addrspace(5)* %value_ptr
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}short_array:
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; R600-VECT: MOVA_INT
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define amdgpu_kernel void @short_array(i32 addrspace(1)* %out, i32 %index) #0 {
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entry:
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%0 = alloca [2 x i16], addrspace(5)
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%1 = getelementptr inbounds [2 x i16], [2 x i16] addrspace(5)* %0, i32 0, i32 0
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%2 = getelementptr inbounds [2 x i16], [2 x i16] addrspace(5)* %0, i32 0, i32 1
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store i16 0, i16 addrspace(5)* %1
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store i16 1, i16 addrspace(5)* %2
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%3 = getelementptr inbounds [2 x i16], [2 x i16] addrspace(5)* %0, i32 0, i32 %index
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%4 = load i16, i16 addrspace(5)* %3
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%5 = sext i16 %4 to i32
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store i32 %5, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}char_array:
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; R600-VECT: MOVA_INT
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define amdgpu_kernel void @char_array(i32 addrspace(1)* %out, i32 %index) #0 {
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entry:
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%0 = alloca [2 x i8], addrspace(5)
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%1 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %0, i32 0, i32 0
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%2 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %0, i32 0, i32 1
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store i8 0, i8 addrspace(5)* %1
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store i8 1, i8 addrspace(5)* %2
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%3 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %0, i32 0, i32 %index
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%4 = load i8, i8 addrspace(5)* %3
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%5 = sext i8 %4 to i32
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store i32 %5, i32 addrspace(1)* %out
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ret void
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}
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; Make sure we don't overwrite workitem information with private memory
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; FUNC-LABEL: {{^}}work_item_info:
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; R600-NOT: MOV T0.X
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; Additional check in case the move ends up in the last slot
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; R600-NOT: MOV * TO.X
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define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) #0 {
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entry:
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%0 = alloca [2 x i32], addrspace(5)
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%1 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 0
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%2 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 1
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store i32 0, i32 addrspace(5)* %1
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store i32 1, i32 addrspace(5)* %2
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%3 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 %in
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%4 = load i32, i32 addrspace(5)* %3
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%5 = call i32 @llvm.r600.read.tidig.x()
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%6 = add i32 %4, %5
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store i32 %6, i32 addrspace(1)* %out
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ret void
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}
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; Test that two stack objects are not stored in the same register
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; The second stack object should be in T3.X
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; FUNC-LABEL: {{^}}no_overlap:
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; R600_CHECK: MOV
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; R600_CHECK: [[CHAN:[XYZW]]]+
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; R600-NOT: [[CHAN]]+
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define amdgpu_kernel void @no_overlap(i32 addrspace(1)* %out, i32 %in) #0 {
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entry:
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%0 = alloca [3 x i8], align 1, addrspace(5)
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%1 = alloca [2 x i8], align 1, addrspace(5)
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%2 = getelementptr inbounds [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 0
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%3 = getelementptr inbounds [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 1
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%4 = getelementptr inbounds [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 2
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%5 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %1, i32 0, i32 0
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%6 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %1, i32 0, i32 1
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store i8 0, i8 addrspace(5)* %2
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store i8 1, i8 addrspace(5)* %3
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store i8 2, i8 addrspace(5)* %4
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store i8 1, i8 addrspace(5)* %5
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store i8 0, i8 addrspace(5)* %6
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%7 = getelementptr inbounds [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 %in
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%8 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %1, i32 0, i32 %in
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%9 = load i8, i8 addrspace(5)* %7
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%10 = load i8, i8 addrspace(5)* %8
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%11 = add i8 %9, %10
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%12 = sext i8 %11 to i32
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store i32 %12, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @char_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
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entry:
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%alloca = alloca [2 x [2 x i8]], addrspace(5)
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%gep0 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
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%gep1 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
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store i8 0, i8 addrspace(5)* %gep0
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store i8 1, i8 addrspace(5)* %gep1
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%gep2 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
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%load = load i8, i8 addrspace(5)* %gep2
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%sext = sext i8 %load to i32
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store i32 %sext, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
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entry:
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%alloca = alloca [2 x [2 x i32]], addrspace(5)
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%gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
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%gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
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store i32 0, i32 addrspace(5)* %gep0
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store i32 1, i32 addrspace(5)* %gep1
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%gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
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%load = load i32, i32 addrspace(5)* %gep2
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store i32 %load, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @i64_array_array(i64 addrspace(1)* %out, i32 %index) #0 {
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entry:
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%alloca = alloca [2 x [2 x i64]], addrspace(5)
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%gep0 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
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%gep1 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
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store i64 0, i64 addrspace(5)* %gep0
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store i64 1, i64 addrspace(5)* %gep1
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%gep2 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
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%load = load i64, i64 addrspace(5)* %gep2
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store i64 %load, i64 addrspace(1)* %out
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ret void
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}
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%struct.pair32 = type { i32, i32 }
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define amdgpu_kernel void @struct_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
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entry:
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%alloca = alloca [2 x [2 x %struct.pair32]], addrspace(5)
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%gep0 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0, i32 1
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%gep1 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1, i32 1
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store i32 0, i32 addrspace(5)* %gep0
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store i32 1, i32 addrspace(5)* %gep1
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%gep2 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index, i32 0
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%load = load i32, i32 addrspace(5)* %gep2
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store i32 %load, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @struct_pair32_array(i32 addrspace(1)* %out, i32 %index) #0 {
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entry:
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%alloca = alloca [2 x %struct.pair32], addrspace(5)
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%gep0 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32] addrspace(5)* %alloca, i32 0, i32 0, i32 1
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%gep1 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32] addrspace(5)* %alloca, i32 0, i32 1, i32 0
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store i32 0, i32 addrspace(5)* %gep0
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store i32 1, i32 addrspace(5)* %gep1
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%gep2 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32] addrspace(5)* %alloca, i32 0, i32 %index, i32 0
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%load = load i32, i32 addrspace(5)* %gep2
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store i32 %load, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @select_private(i32 addrspace(1)* %out, i32 %in) nounwind {
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entry:
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%tmp = alloca [2 x i32], addrspace(5)
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%tmp1 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
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%tmp2 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
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store i32 0, i32 addrspace(5)* %tmp1
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store i32 1, i32 addrspace(5)* %tmp2
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%cmp = icmp eq i32 %in, 0
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%sel = select i1 %cmp, i32 addrspace(5)* %tmp1, i32 addrspace(5)* %tmp2
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%load = load i32, i32 addrspace(5)* %sel
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store i32 %load, i32 addrspace(1)* %out
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ret void
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}
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; AMDGPUPromoteAlloca does not know how to handle ptrtoint. When it
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; finds one, it should stop trying to promote.
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; FUNC-LABEL: ptrtoint:
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; SI-NOT: ds_write
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; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen
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; SI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ;
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define amdgpu_kernel void @ptrtoint(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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%alloca = alloca [16 x i32], addrspace(5)
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%tmp0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %a
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store i32 5, i32 addrspace(5)* %tmp0
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%tmp1 = ptrtoint [16 x i32] addrspace(5)* %alloca to i32
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%tmp2 = add i32 %tmp1, 5
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%tmp3 = inttoptr i32 %tmp2 to i32 addrspace(5)*
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%tmp4 = getelementptr inbounds i32, i32 addrspace(5)* %tmp3, i32 %b
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%tmp5 = load i32, i32 addrspace(5)* %tmp4
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store i32 %tmp5, i32 addrspace(1)* %out
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ret void
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}
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; OPT: !0 = !{i32 0, i32 257}
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; OPT: !1 = !{i32 0, i32 256}
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attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,2" "amdgpu-flat-work-group-size"="1,256" }
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