This website requires JavaScript.
Explore
Help
Sign In
RPCS3
/
llvm-mirror
Watch
1
Star
0
Fork
0
You've already forked llvm-mirror
mirror of
https://github.com/RPCS3/llvm-mirror.git
synced
2024-11-22 10:42:39 +01:00
Code
Issues
Projects
Releases
Wiki
Activity
4f1fd1c209
llvm-mirror
/
lib
/
Target
/
Hexagon
History
Krzysztof Parzyszek
60850cdc6a
[Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs
...
This fixes
https://llvm.org/PR51229
.
2021-07-27 18:36:28 -05:00
..
AsmParser
[llvm] Rename StringRef _lower() method calls to _insensitive()
2021-06-25 00:22:01 +03:00
Disassembler
MCTargetDesc
[llvm] Rename StringRef _lower() method calls to _insensitive()
2021-06-25 00:22:01 +03:00
TargetInfo
BitTracker.cpp
BitTracker.h
CMakeLists.txt
Hexagon.h
Hexagon.td
HexagonArch.h
HexagonAsmPrinter.cpp
HexagonAsmPrinter.h
HexagonBitSimplify.cpp
HexagonBitTracker.cpp
HexagonBitTracker.h
HexagonBlockRanges.cpp
HexagonBlockRanges.h
HexagonBranchRelaxation.cpp
HexagonCallingConv.td
HexagonCFGOptimizer.cpp
HexagonCommonGEP.cpp
[Hexagon] Opaquify pointer usage in GEP commoning
2021-06-24 16:06:36 -05:00
HexagonConstExtenders.cpp
HexagonConstPropagation.cpp
HexagonCopyToCombine.cpp
HexagonDepArch.h
HexagonDepArch.td
HexagonDepDecoders.inc
HexagonDepIICHVX.td
HexagonDepIICScalar.td
HexagonDepInstrFormats.td
HexagonDepInstrInfo.td
HexagonDepITypes.h
HexagonDepITypes.td
HexagonDepMapAsm2Intrin.td
HexagonDepMappings.td
HexagonDepMask.h
HexagonDepOperands.td
HexagonDepTimingClasses.h
HexagonEarlyIfConv.cpp
HexagonExpandCondsets.cpp
HexagonFixupHwLoops.cpp
HexagonFrameLowering.cpp
Rename MachineMemOperand::getOrdering -> getSuccessOrdering.
2021-06-21 16:49:27 -07:00
HexagonFrameLowering.h
HexagonGenExtract.cpp
HexagonGenInsert.cpp
HexagonGenMux.cpp
HexagonGenPredicate.cpp
HexagonHardwareLoops.cpp
[Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs
2021-07-27 18:36:28 -05:00
HexagonHazardRecognizer.cpp
HexagonHazardRecognizer.h
HexagonIICHVX.td
HexagonIICScalar.td
HexagonInstrFormats.td
HexagonInstrFormatsV60.td
HexagonInstrFormatsV65.td
HexagonInstrInfo.cpp
HexagonInstrInfo.h
HexagonIntrinsics.td
HexagonIntrinsicsV5.td
HexagonIntrinsicsV60.td
HexagonISelDAGToDAG.cpp
HexagonISelDAGToDAG.h
HexagonISelDAGToDAGHVX.cpp
HexagonISelLowering.cpp
[Hexagon] Generate trap/undef if misaligned access is detected
2021-07-06 14:52:23 -05:00
HexagonISelLowering.h
[Hexagon] Generate trap/undef if misaligned access is detected
2021-07-06 14:52:23 -05:00
HexagonISelLoweringHVX.cpp
HexagonLoopIdiomRecognition.cpp
HexagonLoopIdiomRecognition.h
HexagonMachineFunctionInfo.cpp
HexagonMachineFunctionInfo.h
HexagonMachineScheduler.cpp
HexagonMachineScheduler.h
HexagonMapAsm2IntrinV62.gen.td
HexagonMCInstLower.cpp
HexagonNewValueJump.cpp
HexagonOperands.td
HexagonOptAddrMode.cpp
HexagonOptimizeSZextends.cpp
HexagonPatterns.td
[Hexagon] Add patterns to load i1
2021-06-28 12:17:30 -05:00
HexagonPatternsHVX.td
HexagonPatternsV65.td
HexagonPeephole.cpp
HexagonPseudo.td
HexagonRDFOpt.cpp
HexagonRegisterInfo.cpp
HexagonRegisterInfo.h
HexagonRegisterInfo.td
HexagonSchedule.td
HexagonScheduleV5.td
HexagonScheduleV55.td
HexagonScheduleV60.td
HexagonScheduleV62.td
HexagonScheduleV65.td
HexagonScheduleV66.td
HexagonScheduleV67.td
HexagonScheduleV67T.td
HexagonScheduleV68.td
HexagonSelectionDAGInfo.cpp
HexagonSelectionDAGInfo.h
HexagonSplitConst32AndConst64.cpp
HexagonSplitDouble.cpp
HexagonStoreWidening.cpp
HexagonSubtarget.cpp
HexagonSubtarget.h
[Hexagon] Convert getTypeAlignment to return Align
2021-06-25 10:53:14 -05:00
HexagonTargetMachine.cpp
HexagonTargetMachine.h
HexagonTargetObjectFile.cpp
HexagonTargetObjectFile.h
HexagonTargetStreamer.h
HexagonTargetTransformInfo.cpp
HexagonTargetTransformInfo.h
HexagonVectorCombine.cpp
[IRBuilder] Add type argument to CreateMaskedLoad/Gather
2021-07-04 12:17:59 +02:00
HexagonVectorLoopCarriedReuse.cpp
HexagonVectorLoopCarriedReuse.h
HexagonVectorPrint.cpp
HexagonVExtract.cpp
HexagonVLIWPacketizer.cpp
HexagonVLIWPacketizer.h
RDFCopy.cpp
RDFCopy.h
RDFDeadCode.cpp
RDFDeadCode.h