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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-23 21:13:02 +02:00
llvm-mirror/test/CodeGen/MIR/ARM
Tim Northover d33c3d2654 ARM: fix handling of SUB immediates in peephole opt.
We were negating an immediate that was going to be used in a SUBri form
unnecessarily. Since ADD/SUB are very similar we *can* do that, but we have to
change the SUB to an ADD at the same time. This also applies to ADD, and allows
us to handle a slightly larger range of immediates for those two operations.

rdar://25992245

llvm-svn: 268276
2016-05-02 18:30:08 +00:00
..
ARMLoadStoreDBG.mir tests: tweak MIR for ARM tests to correct MI issues 2016-04-26 17:54:21 +00:00
bundled-instructions.mir When printing MIR, output to errs() rather than outs(). 2016-02-19 00:18:46 +00:00
cfi-same-value.mir When printing MIR, output to errs() rather than outs(). 2016-02-19 00:18:46 +00:00
expected-closing-brace.mir
extraneous-closing-brace-error.mir
imm-peephole-arm.mir ARM: fix handling of SUB immediates in peephole opt. 2016-05-02 18:30:08 +00:00
imm-peephole-thumb.mir ARM: fix handling of SUB immediates in peephole opt. 2016-05-02 18:30:08 +00:00
lit.local.cfg
nested-instruction-bundle-error.mir
sched-it-debug-nodes.mir tests: tweak MIR for ARM tests to correct MI issues 2016-04-26 17:54:21 +00:00