Hsiangkai Wang fc3df54f27 [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame. ... It is necessary to generate fixups in .debug_frame or .eh_frame as relaxation is enabled due to the address delta may be changed after relaxation. There is an opcode with 6-bits data in debug frame encoding. So, we also need 6-bits fixup types. Differential Revision: https://reviews.llvm.org/D58335 llvm-svn: 366524		2019-07-19 02:03:34 +00:00
..
AsmParser	[RISCV] Allow parsing dot '.' in assembly	2019-07-12 08:36:07 +00:00
Disassembler	Revert CMake: Make most target symbols hidden by default	2019-06-11 03:21:13 +00:00
MCTargetDesc	[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.	2019-07-19 02:03:34 +00:00
TargetInfo	Revert CMake: Make most target symbols hidden by default	2019-06-11 03:21:13 +00:00
Utils	[RISCV] Avoid signed integer overflow UB in RISCVMatInt::generateInstSeq	2019-07-18 04:02:58 +00:00
CMakeLists.txt	[RISCV] Add RISCV-specific TargetTransformInfo	2019-06-21 13:36:09 +00:00
LLVMBuild.txt	[RISCV] Add RISCV-specific TargetTransformInfo	2019-06-21 13:36:09 +00:00
RISCV.h
RISCV.td	[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references	2019-07-05 12:16:40 +00:00
RISCVAsmPrinter.cpp	[RISCV] Support z and i operand modifiers	2019-07-08 05:00:26 +00:00
RISCVCallingConv.td	[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs	2019-03-30 17:59:30 +00:00
RISCVExpandPseudoInsts.cpp	[RISCV] Add lowering of global TLS addresses	2019-06-19 08:40:59 +00:00
RISCVFrameLowering.cpp	[RISCV] Add CFI directives for RISCV prologue/epilog.	2019-06-12 03:04:22 +00:00
RISCVFrameLowering.h
RISCVInstrFormats.td
RISCVInstrFormatsC.td
RISCVInstrInfo.cpp	[RISCV] Don't acccess an invalidated iterator in RISCVInstrInfo::removeBranch	2019-07-18 03:23:47 +00:00
RISCVInstrInfo.h
RISCVInstrInfo.td	[RISCV] Match GNU tools canonical JALR and add aliases	2019-07-16 04:56:43 +00:00
RISCVInstrInfoA.td	[RISCV][NFC] Fix HasStedExtA -> HasStdExtA typo in comment	2019-07-16 03:54:08 +00:00
RISCVInstrInfoC.td
RISCVInstrInfoD.td	[RISCV] Add seto pattern expansion	2019-04-01 09:54:14 +00:00
RISCVInstrInfoF.td	[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references	2019-07-05 12:16:40 +00:00
RISCVInstrInfoM.td
RISCVISelDAGToDAG.cpp	[RISCV] Support @llvm.readcyclecounter() Intrinsic	2019-07-05 12:35:21 +00:00
RISCVISelLowering.cpp	[RISCV] Reset NoPHIS MachineFunctionProperty in emitSelectPseudo	2019-07-18 07:52:41 +00:00
RISCVISelLowering.h	[RISCV] Specify registers used in DWARF exception handling	2019-07-08 09:16:47 +00:00
RISCVMachineFunctionInfo.h	[RISCV] Delete a ctor that is commented out. NFC	2019-07-05 08:25:14 +00:00
RISCVMCInstLower.cpp	[RISCV] Add lowering of global TLS addresses	2019-06-19 08:40:59 +00:00
RISCVMergeBaseOffset.cpp
RISCVRegisterInfo.cpp	CodeGen: Introduce a class for registers	2019-06-24 15:50:29 +00:00
RISCVRegisterInfo.h	CodeGen: Introduce a class for registers	2019-06-24 15:50:29 +00:00
RISCVRegisterInfo.td
RISCVSubtarget.cpp	[RISCV] Add basic RV32E definitions and MC layer support	2019-03-22 11:21:40 +00:00
RISCVSubtarget.h	[RISCV] Add basic RV32E definitions and MC layer support	2019-03-22 11:21:40 +00:00
RISCVSystemOperands.td	[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references	2019-07-05 12:16:40 +00:00
RISCVTargetMachine.cpp	[RISCV] Add RISCV-specific TargetTransformInfo	2019-06-21 13:36:09 +00:00
RISCVTargetMachine.h	[RISCV] Add RISCV-specific TargetTransformInfo	2019-06-21 13:36:09 +00:00
RISCVTargetObjectFile.cpp	[RISCV] Put data smaller than eight bytes to small data section	2019-04-11 04:59:13 +00:00
RISCVTargetObjectFile.h	[RISCV] Put data smaller than eight bytes to small data section	2019-04-11 04:59:13 +00:00
RISCVTargetTransformInfo.cpp	[RISCV] Fix RISCVTTIImpl::getIntImmCost for immediates where getMinSignedBits() > 64	2019-07-09 10:56:18 +00:00
RISCVTargetTransformInfo.h	[RISCV] Add RISCV-specific TargetTransformInfo	2019-06-21 13:36:09 +00:00