Oliver Stannard 5be239fc50 [AArch64][v8.5A] Add Branch Target Identification instructions ... This adds new instructions used by the Branch Target Identification feature. When this is enabled, these are the only instructions which can be targeted by indirect branch instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52485 llvm-svn: 343225		2018-09-27 14:54:33 +00:00
..
AsmParser	[AArch64][v8.5A] Add Branch Target Identification instructions	2018-09-27 14:54:33 +00:00
Disassembler	[AArch64][v8.5A] Add speculation restriction system registers	2018-09-27 14:05:46 +00:00
InstPrinter	[AArch64][v8.5A] Add Branch Target Identification instructions	2018-09-27 14:54:33 +00:00
MCTargetDesc	NFC: use bit_cast more in AArch64AddressingModes	2018-09-11 04:08:05 +00:00
TargetInfo
Utils	[AArch64][v8.5A] Add Branch Target Identification instructions	2018-09-27 14:54:33 +00:00
AArch64.h
AArch64.td	[AArch64][v8.5A] Add Branch Target Identification instructions	2018-09-27 14:54:33 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp	llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...)	2018-09-27 02:13:45 +00:00
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp	[COFF] Hoist constant pool handling from X86AsmPrinter into AsmPrinter	2018-07-25 18:35:31 +00:00
AArch64CallingConvention.h
AArch64CallingConvention.td	[AArch64] Implement aarch64_vector_pcs codegen support.	2018-09-12 12:10:22 +00:00
AArch64CallLowering.cpp	[AArch64] Support adding X[8-15,18] registers as CSRs.	2018-09-22 22:17:50 +00:00
AArch64CallLowering.h	[GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value	2018-08-02 08:33:31 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandPseudoInsts.cpp	[AArch64] Add Tiny Code Model for AArch64	2018-08-22 11:31:39 +00:00
AArch64FalkorHWPFFix.cpp
AArch64FastISel.cpp	[AArch64] Support adding X[8-15,18] registers as CSRs.	2018-09-22 22:17:50 +00:00
AArch64FrameLowering.cpp	Reapply changes reverted in r343114, lldb patch to follow shortly	2018-09-27 10:39:20 +00:00
AArch64FrameLowering.h
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td
AArch64InstrFormats.td	[AArch64][v8.5A] Add Branch Target Identification instructions	2018-09-27 14:54:33 +00:00
AArch64InstrInfo.cpp	[MinGW] [AArch64] Add stubs for potential automatic dllimported variables	2018-09-04 20:56:21 +00:00
AArch64InstrInfo.h	[MachineOutliner][AArch64] Add support for saving LR to a register	2018-07-30 17:45:28 +00:00
AArch64InstrInfo.td	[AArch64][v8.5A] Add Branch Target Identification instructions	2018-09-27 14:54:33 +00:00
AArch64InstructionSelector.cpp	[AArch64] Add Tiny Code Model for AArch64	2018-08-22 11:31:39 +00:00
AArch64ISelDAGToDAG.cpp	[AArch64][v8.5A] Add speculation restriction system registers	2018-09-27 14:05:46 +00:00
AArch64ISelLowering.cpp	[AArch64] Share search bookkeeping in combines. NFCI.	2018-09-25 15:30:22 +00:00
AArch64ISelLowering.h	[AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR	2018-09-19 14:51:42 +00:00
AArch64LegalizerInfo.cpp	[AArch64][GlobalISel] Make G_BLOCK_ADDR legal.	2018-07-31 00:08:56 +00:00
AArch64LegalizerInfo.h
AArch64LoadStoreOptimizer.cpp	[MI] Change the array of MachineMemOperand pointers to be	2018-08-16 21:30:05 +00:00
AArch64MachineFunctionInfo.h	Remove trailing space	2018-07-30 19:41:25 +00:00
AArch64MacroFusion.cpp	AArch64: Add FuseCryptoEOR fusion rules	2018-09-19 20:50:51 +00:00
AArch64MacroFusion.h
AArch64MCInstLower.cpp	[MinGW] [AArch64] Add stubs for potential automatic dllimported variables	2018-09-04 20:56:21 +00:00
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp
AArch64RegisterBankInfo.cpp
AArch64RegisterBankInfo.h
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp	[Aarch64] Fix memcpy that was copying 4x too many bytes	2018-09-23 18:43:28 +00:00
AArch64RegisterInfo.h	[AArch64] Support adding X[8-15,18] registers as CSRs.	2018-09-22 22:17:50 +00:00
AArch64RegisterInfo.td	[AArch64][SVE] Asm: Add MOVPRFX instructions.	2018-07-30 15:42:46 +00:00
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64SchedExynosM1.td
AArch64SchedExynosM3.td
AArch64SchedFalkor.td
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td
AArch64SchedKryoDetails.td
AArch64SchedThunderX2T99.td
AArch64SchedThunderX.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64SIMDInstrOpt.cpp
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp	[AArch64] Support adding X[8-15,18] registers as CSRs.	2018-09-22 22:17:50 +00:00
AArch64Subtarget.h	[AArch64][v8.5A] Add Branch Target Identification instructions	2018-09-27 14:54:33 +00:00
AArch64SVEInstrInfo.td	[AArch64][SVE] Asm: Enable instructions to be prefixed.	2018-07-30 16:05:45 +00:00
AArch64SystemOperands.td	[AArch64][v8.5A] Add Branch Target Identification instructions	2018-09-27 14:54:33 +00:00
AArch64TargetMachine.cpp	[AArch64] Add Tiny Code Model for AArch64	2018-08-22 11:31:39 +00:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp	[AArch64] DWARF: do not generate AT_location for thread local	2018-08-01 23:46:49 +00:00
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp	Remove trailing space	2018-07-30 19:41:25 +00:00
AArch64TargetTransformInfo.h
CMakeLists.txt
LLVMBuild.txt
SVEInstrFormats.td	[AArch64][SVE] Asm: Enable instructions to be prefixed.	2018-07-30 16:05:45 +00:00