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f58aee7cea
Summary: Also explicitly port over some tests in llvm.amdgcn.image.* that were missing. Some tests are removed because they no longer apply (i.e. explicitly testing building an address vector via insertelement). This is in preparation for the eventual removal of the old-style intrinsics. Some additional notes: - constant-address-space-32bit.ll: change some GCN-NEXT to GCN because the instruction schedule was subtly altered - insert_vector_elt.ll: the old test didn't actually test anything, because %tmp1 was not used; remove the load, because it doesn't work (Because of the amdgpu_ps calling convention? In any case, it's orthogonal to what the test claims to be testing.) Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf Reviewers: arsenm, rampitec Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D48018 llvm-svn: 335229
85 lines
3.9 KiB
LLVM
85 lines
3.9 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}adjust_writemask_crash_0_nochain:
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; GCN: image_get_lod v0, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} dmask:0x2
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; GCN-NOT: v1
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; GCN-NOT: v0
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; GCN: buffer_store_dword v0
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define amdgpu_ps void @adjust_writemask_crash_0_nochain() #0 {
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main_body:
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%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
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%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
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%tmp4 = extractelement <4 x float> %tmp3, i32 0
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store volatile float %tmp4, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}adjust_writemask_crash_1_nochain:
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; GCN: image_get_lod v0, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} dmask:0x1
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; GCN-NOT: v1
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; GCN-NOT: v0
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; GCN: buffer_store_dword v0
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define amdgpu_ps void @adjust_writemask_crash_1_nochain() #0 {
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main_body:
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%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
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%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 0, i32 undef, i32 undef>
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%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
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%tmp4 = extractelement <4 x float> %tmp3, i32 1
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store volatile float %tmp4, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}adjust_writemask_crash_0_chain:
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; GCN: image_sample v0, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} dmask:0x2
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; GCN-NOT: v1
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; GCN-NOT: v0
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; GCN: buffer_store_dword v0
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define amdgpu_ps void @adjust_writemask_crash_0_chain() #0 {
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main_body:
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%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
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%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
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%tmp4 = extractelement <4 x float> %tmp3, i32 0
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store volatile float %tmp4, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}adjust_writemask_crash_1_chain:
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; GCN: image_sample v0, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} dmask:0x1
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; GCN-NOT: v1
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; GCN-NOT: v0
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; GCN: buffer_store_dword v0
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define amdgpu_ps void @adjust_writemask_crash_1_chain() #0 {
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main_body:
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%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
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%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 0, i32 undef, i32 undef>
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%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
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%tmp4 = extractelement <4 x float> %tmp3, i32 1
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store volatile float %tmp4, float addrspace(1)* undef
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ret void
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}
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define amdgpu_ps void @adjust_writemask_crash_0_v4() #0 {
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main_body:
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%tmp = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 5, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
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%tmp1 = bitcast <4 x float> %tmp to <4 x i32>
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%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
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%tmp4 = extractelement <4 x float> %tmp3, i32 0
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store volatile float %tmp4, float addrspace(1)* undef
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ret void
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}
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declare <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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