..
GlobalISel
Revert "AMDGPU/GlobalISel: Implement select for G_INSERT"
2018-10-11 23:36:46 +00:00
32-bit-local-address-space.ll
add_i1.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
add_i64.ll
add_i128.ll
add-debug.ll
add.i16.ll
add.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
add.v2i16.ll
addrspacecast-captured.ll
addrspacecast-constantexpr.ll
addrspacecast.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
adjust-writemask-invalid-copy.ll
alignbit-pat.ll
alloca.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
always-uniform.ll
amdgcn.bitcast.ll
amdgcn.private-memory.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
amdgpu-alias-analysis.ll
Allow subclassing ExternalAA
2018-11-07 20:26:42 +00:00
amdgpu-codegenprepare-fdiv.ll
amdgpu-codegenprepare-i16-to-i32.ll
amdgpu-codegenprepare-idiv.ll
amdgpu-inline.ll
amdgpu-shader-calling-convention.ll
amdgpu.private-memory.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
amdgpu.work-item-intrinsics.deprecated.ll
amdhsa-trap-num-sgprs.ll
amdpal_scratch_mergedshader.ll
amdpal-cs.ll
amdpal-es.ll
amdpal-gs.ll
amdpal-hs.ll
amdpal-ls.ll
amdpal-ps.ll
amdpal-psenable.ll
amdpal-vs.ll
amdpal.ll
and-gcn.ll
and.ll
annotate-kernel-features-hsa-call.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
annotate-kernel-features-hsa.ll
annotate-kernel-features.ll
anonymous-gv.ll
any_extend_vector_inreg.ll
anyext.ll
array-ptr-calc-i32.ll
array-ptr-calc-i64.ll
ashr.v2i16.ll
atomic_cmp_swap_local.ll
atomic_load_add.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_load_local.ll
atomic_load_sub.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_optimizations_buffer.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_optimizations_global_pointer.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_optimizations_local_pointer.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_optimizations_pixelshader.ll
[AMDGPU] Fix the new atomic optimizer in pixel shaders.
2018-11-05 12:04:48 +00:00
atomic_optimizations_raw_buffer.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_optimizations_struct_buffer.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
atomic_store_local.ll
atomicrmw-nand.ll
AMDGPU: Expand atomicrmw nand in IR
2018-10-02 03:50:56 +00:00
attr-amdgpu-flat-work-group-size.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
attr-amdgpu-num-sgpr-spill-to-smem.ll
attr-amdgpu-num-sgpr.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
attr-amdgpu-num-vgpr.ll
attr-amdgpu-waves-per-eu.ll
attr-unparseable.ll
barrier-elimination.ll
basic-branch.ll
basic-call-return.ll
basic-loop.ll
bfe_uint.ll
bfe-combine.ll
bfe-patterns.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
bfi_int.ll
bfm.ll
big_alu.ll
bitcast-constant-to-vector.ll
AMDGPU: Fix assertion with bitcast from i64 constant to v4i16
2018-11-02 02:43:55 +00:00
bitcast-vector-extract.ll
bitreverse-inline-immediates.ll
bitreverse.ll
br_cc.f16.ll
branch-condition-and.ll
branch-relax-bundle.ll
branch-relax-spill.ll
AMDGPU: Use scavengeRegisterBackwards
2018-10-30 01:33:14 +00:00
branch-relaxation.ll
AMDGPU: Use scavengeRegisterBackwards
2018-10-30 01:33:14 +00:00
branch-uniformity.ll
break-smem-soft-clauses.mir
break-vmem-soft-clauses.mir
bswap.ll
buffer-schedule.ll
bug-vopc-commute.ll
build_vector.ll
build-vector-insert-elt-infloop.ll
[LICM] Use ICFLoopSafetyInfo in LICM
2018-11-06 02:44:49 +00:00
build-vector-packed-partial-undef.ll
byval-frame-setup.ll
AMDGPU: Fix private handling for allowsMisalignedMemoryAccesses
2018-09-24 13:18:15 +00:00
call_fs.ll
call-argument-types.ll
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
2018-10-30 15:04:40 +00:00
call-constexpr.ll
[AMDGPU] Add a pass to promote bitcast calls
2018-10-26 13:18:36 +00:00
call-encoding.ll
call-graph-register-usage.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
call-preserved-registers.ll
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
2018-10-30 15:04:40 +00:00
call-return-types.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
callee-frame-setup.ll
callee-special-input-sgprs.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
callee-special-input-vgprs.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
calling-conventions.ll
captured-frame-index.ll
cayman-loop-bug.ll
cf_end.ll
cf-loop-on-constant.ll
cf-stack-bug.ll
cgp-addressing-modes-flat.ll
cgp-addressing-modes.ll
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
cgp-bitfield-extract.ll
clamp-modifier.ll
clamp-omod-special-case.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
clamp.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
cluster-flat-loads-postra.mir
cluster-flat-loads.mir
cndmask-no-def-vcc.ll
coalescer_distribute.ll
coalescer_remat.ll
coalescer-extend-pruned-subrange.mir
coalescer-identical-values-undef.mir
coalescer-subranges-another-copymi-not-live.mir
coalescer-subranges-another-prune-error.mir
coalescer-subreg-join.mir
coalescer-subregjoin-fullcopy.mir
coalescer-with-subregs-bad-identical.mir
coalescing-with-subregs-in-loop-bug.mir
code-object-v3.ll
AMDGPU: Rename isAmdCodeObjectV2 -> isAmdHsaOrMesa
2018-10-04 21:02:16 +00:00
codegen-prepare-addrmode-sext.ll
collapse-endcf.ll
combine_vloads.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
combine-and-sext-bool.ll
combine-cond-add-sub.ll
combine-ftrunc.ll
comdat.ll
commute_modifiers.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
commute-compares.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
commute-shifts.ll
complex-folding.ll
concat_vectors.ll
constant-address-space-32bit.ll
AMDGPU: Handle 32-bit address wraparounds for SMRD opcodes
2018-08-29 20:03:00 +00:00
constant-fold-imm-immreg.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
constant-fold-mi-operands.ll
control-flow-fastregalloc.ll
RegAllocFast: Leave unassigned virtreg entries in map
2018-11-07 06:57:03 +00:00
control-flow-optnone.ll
convergent-inlineasm.ll
copy-illegal-type.ll
[DAGCombiner][AMDGPU][Mips] Fold bitcast with volatile loads if the resulting load is legal for the target.
2018-08-28 03:47:20 +00:00
copy-to-reg.ll
couldnt-join-subrange-3.mir
cross-block-use-is-not-abi-copy.ll
DAG: Don't use ABI copies in some contexts
2018-08-30 05:49:28 +00:00
ctlz_zero_undef.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
ctlz.ll
ctpop16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
ctpop64.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
ctpop.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
cttz_zero_undef.ll
cube.ll
cvt_f32_ubyte.ll
cvt_flr_i32_f32.ll
cvt_rpi_i32_f32.ll
dag-divergence.ll
AMDGPU: Fix DAG divergence not reporting flat loads
2018-09-04 18:58:19 +00:00
dagcomb-shuffle-vecextend-non2.ll
dagcombine-reassociate-bug.ll
dagcombine-select.ll
dagcombine-setcc-select.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
dagcombiner-bug-illegal-vec4-int-to-fp.ll
dead_copy.mir
debug-value2.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
debug-value.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
debug.ll
debugger-emit-prologue.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
debugger-insert-nops.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
default-fp-mode.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
detect-dead-lanes.mir
directive-amdgcn-target.ll
AMDGPU: Add sram-ecc feature
2018-11-05 22:44:19 +00:00
disconnected-predset-break-bug.ll
div_i128.ll
diverge-extra-formal-args.ll
diverge-interp-mov-lower.ll
diverge-switch-default.ll
[AMDGPU] restore r342722 which was reverted with r342743
2018-09-25 09:39:21 +00:00
divrem24-assume.ll
drop-mem-operand-move-smrd.ll
ds_read2_offset_order.ll
ds_read2_superreg.ll
ds_read2.ll
ds_read2st64.ll
ds_write2.ll
ds_write2st64.ll
ds-combine-large-stride.ll
ds-negative-offset-addressing-mode-loop.ll
ds-sub-offset.ll
dynamic_stackalloc.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
early-if-convert-cost.ll
early-if-convert.ll
early-inline-alias.ll
early-inline.ll
elf-header-flags-mach.ll
AMDGPU: Add sram-ecc feature
2018-11-05 22:44:19 +00:00
elf-header-flags-sram-ecc.ll
AMDGPU: Add sram-ecc feature
2018-11-05 22:44:19 +00:00
elf-header-flags-xnack.ll
elf-header-osabi.ll
elf-notes.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
elf.ll
elf.r600.ll
else.ll
empty-function.ll
enable-no-signed-zeros-fp-math.ll
endcf-loop-header.ll
endpgm-dce.mir
AMDGPU: Don't delete instructions if S_ENDPGM has implicit uses
2018-08-28 18:55:55 +00:00
enqueue-kernel.ll
exceed-max-sgprs.ll
extend-bit-ops-i16.ll
extload-align.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
extload-private.ll
extload.ll
extract_vector_elt-f16.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
extract_vector_elt-f64.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
extract_vector_elt-i8.ll
extract_vector_elt-i16.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
extract_vector_elt-i64.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
extract-lowbits.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
extract-subvector-equal-length.ll
extract-vector-elt-build-vector-combine.ll
extractelt-to-trunc.ll
fabs.f16.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
fabs.f64.ll
fabs.ll
fadd64.ll
fadd-fma-fmul-combine.ll
fadd.f16.ll
fadd.ll
fcanonicalize-elimination.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fcanonicalize.f16.ll
DAG: Handle odd vector sizes in calling conv splitting
2018-09-10 11:49:23 +00:00
fcanonicalize.ll
AMDGPU: Expand vector canonicalizes
2018-09-18 01:51:33 +00:00
fceil64.ll
fceil.ll
fcmp64.ll
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.f16.ll
fcmp.ll
fconst64.ll
fcopysign.f16.ll
fcopysign.f32.ll
fcopysign.f64.ll
fdiv32-to-rcp-folding.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
fdiv.f16.ll
fdiv.f64.ll
fdiv.ll
fdot2.ll
fence-barrier.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
fetch-limits.r600.ll
fetch-limits.r700+.ll
fexp.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
ffloor.f64.ll
ffloor.ll
fix-vgpr-copies.mir
fix-wwm-liveness.mir
flat_atomics_i64.ll
flat_atomics.ll
flat-address-space.ll
flat-for-global-subtarget-feature.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
flat-load-clustering.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
flat-scratch-reg.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
floor.ll
fma-combine.ll
fma.f64.ll
fma.ll
fmad.ll
fmax3.f64.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmax3.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmax_legacy.f16.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmax_legacy.f64.ll
fmax_legacy.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmax.ll
fmaxnum.f64.ll
fmaxnum.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmaxnum.r600.ll
fmed3.ll
AMDGPU: Don't form fmed3 if it will require materialization
2018-09-18 02:34:54 +00:00
fmin3.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmin_fmax_legacy.amdgcn.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmin_legacy.f16.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmin_legacy.f64.ll
fmin_legacy.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fmin.ll
fminnum.f64.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fminnum.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fminnum.r600.ll
fmul64.ll
fmul-2-combine-multi-use.ll
fmul.f16.ll
fmul.ll
fmuladd.f16.ll
fmuladd.f32.ll
fmuladd.f64.ll
fmuladd.v2f16.ll
fnearbyint.ll
fneg-combines.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
fneg-combines.si.ll
fneg-fabs.f16.ll
fneg-fabs.f64.ll
fneg-fabs.ll
fneg.f16.ll
fneg.f64.ll
fneg.ll
fold-cndmask.mir
fold-fmul-to-neg-abs.ll
fold-imm-copy.mir
[AMDGPU] Preliminary patch for divergence driven instruction selection. Operands Folding 1.
2018-08-30 13:55:04 +00:00
fold-imm-f16-f32.mir
fold-immediate-operand-shrink-with-carry.mir
MachineOperand/MIParser: Do not print debug-use flag, infer it
2018-10-30 23:28:27 +00:00
fold-immediate-operand-shrink.mir
Don't count debug instructions towards neighborhood count
2018-08-30 07:18:19 +00:00
fold-immediate-output-mods.mir
fold-implicit-operand.mir
fold-multiple.mir
fold-operands-order.mir
fold-vgpr-copy.mir
[AMDGPU] Fold copy (copy vgpr)
2018-09-27 18:55:20 +00:00
force-alwaysinline-lds-global-address-codegen.ll
AMDGPU: Always run AMDGPUAlwaysInline
2018-10-03 02:47:25 +00:00
force-alwaysinline-lds-global-address.ll
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
fp16_to_fp32.ll
fp16_to_fp64.ll
fp32_to_fp16.ll
fp_to_sint.f64.ll
fp_to_sint.ll
fp_to_uint.f64.ll
fp_to_uint.ll
fp-classify.ll
fpext-free.ll
fpext.f16.ll
fpext.ll
fptosi.f16.ll
fptoui.f16.ll
fptrunc.f16.ll
fptrunc.ll
fract.f64.ll
fract.ll
frame-index-elimination.ll
frem.ll
fsqrt.f64.ll
fsqrt.ll
fsub64.ll
fsub.f16.ll
fsub.ll
ftrunc.f64.ll
ftrunc.ll
function-args.ll
DAG: Handle odd vector sizes in calling conv splitting
2018-09-10 11:49:23 +00:00
function-returns.ll
DAG: Handle odd vector sizes in calling conv splitting
2018-09-10 11:49:23 +00:00
gep-address-space.ll
gfx902-without-xnack.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
global_atomics_i64.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
global_atomics.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
global_smrd_cfg.ll
global_smrd.ll
AMDGPU: Use GOT PSV since it has an address space now
2018-09-10 02:23:39 +00:00
global-constant.ll
global-directive.ll
global-extload-i16.ll
global-smrd-unknown.ll
global-variable-relocs.ll
gv-const-addrspace.ll
gv-offset-folding.ll
half.ll
hazard-buffer-store-v-interp.mir
hazard-inlineasm.mir
hazard.mir
[AMDGPU] Prevent sequences of non-instructions disrupting GCNHazardRecognizer wait state counting
2018-09-10 10:14:48 +00:00
hoist-cond.ll
hsa-default-device.ll
hsa-fp-mode.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
hsa-func-align.ll
hsa-func.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
hsa-globals.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
hsa-group-segment.ll
hsa-metadata-deduce-ro-arg.ll
hsa-metadata-enqueue-kernel.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
hsa-metadata-from-llvm-ir-full.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
hsa-metadata-hidden-args.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
hsa-metadata-images.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
hsa-metadata-invalid-ocl-version-1.ll
hsa-metadata-invalid-ocl-version-2.ll
hsa-metadata-invalid-ocl-version-3.ll
hsa-metadata-kernel-code-props.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
hsa-metadata-kernel-debug-props.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
hsa-note-no-func.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
hsa.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
huge-private-buffer.ll
i1-copy-from-loop.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
i1-copy-implicit-def.ll
i1-copy-phi-uniform-branch.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
i1-copy-phi.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
i8-to-double-to-float.ll
icmp64.ll
icmp-select-sete-reverse-args.ll
icmp.i16.ll
idiv-licm.ll
idot2.ll
AMDGPU: Actually commit re-run of update_llc_test_checks
2018-08-31 15:05:06 +00:00
idot4.ll
[AMDGPU] Match signed dot4/8 pattern.
2018-10-04 16:57:37 +00:00
idot8.ll
[AMDGPU] Handle the idot8 pattern generated by FE.
2018-11-01 22:48:19 +00:00
illegal-sgpr-to-vgpr-copy.ll
image-attributes.ll
image-resource-id.ll
image-schedule.ll
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
imm16.ll
imm.ll
immv216.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
indirect-addressing-si-noopt.ll
indirect-addressing-si.ll
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
2018-10-30 15:04:40 +00:00
indirect-private-64.ll
infer-addrpace-pipeline.ll
infinite-loop-evergreen.ll
infinite-loop.ll
inline-asm.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
inline-attr.ll
inline-calls.ll
inline-constraints.ll
inlineasm-16.ll
inlineasm-illegal-type.ll
inlineasm-packed.ll
InlineAsmCrash.ll
input-mods.ll
insert_subreg.ll
insert_vector_elt.ll
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
2018-10-30 15:04:40 +00:00
insert_vector_elt.v2i16.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
insert-skips-kill-uncond.mir
insert-waitcnts-callee.mir
insert-waitcnts-exp.mir
inserted-wait-states.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
internalize.ll
AMDGPU: Stop forcing internalize at -O0
2018-08-31 06:02:36 +00:00
invalid-addrspacecast.ll
AMDGPU: Stop reporting is-noop addrspacecast for constant 32-bit
2018-09-10 11:59:27 +00:00
invalid-alloca.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
invariant-load-no-alias-store.ll
invert-br-undef-vcc.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
ipra.ll
jump-address.ll
kcache-fold.ll
kernarg-stack-alignment.ll
kernel-args.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
kernel-argument-dag-lowering.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
known-never-nan.ll
DAG: Handle extract_vector_elt in isKnownNeverNaN
2018-09-03 14:01:03 +00:00
known-never-snan.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
knownbits-recursion.ll
large-alloca-compute.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
large-alloca-graphics.ll
large-constant-initializer.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
large-work-group-promote-alloca.ll
lds_atomic_f32.ll
lds-alignment.ll
lds-bounds.ll
AMDGPU: Avoid selecting ds_{read,write}2_b32 on SI
2018-10-17 15:37:48 +00:00
lds-global-non-entry-func.ll
lds-initializer.ll
lds-m0-init-in-loop.ll
lds-oqap-crash.ll
lds-output-queue.ll
lds-size.ll
lds-zero-initializer.ll
legalize-fp-load-invariant.ll
[AMDGPU] Rename pass "isel" to "amdgpu-isel"
2018-10-03 03:38:22 +00:00
legalizedag-bug-expand-setcc.ll
limit-coalesce.mir
lit.local.cfg
literals.ll
liveness.mir
llvm.amdgcn.alignb.ll
llvm.amdgcn.atomic.dec.ll
llvm.amdgcn.atomic.inc.ll
llvm.amdgcn.buffer.atomic.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
llvm.amdgcn.buffer.load.format.d16.ll
llvm.amdgcn.buffer.load.format.ll
llvm.amdgcn.buffer.load.ll
llvm.amdgcn.buffer.store.format.d16.ll
llvm.amdgcn.buffer.store.format.ll
llvm.amdgcn.buffer.store.ll
llvm.amdgcn.buffer.wbinvl1.ll
llvm.amdgcn.buffer.wbinvl1.sc.ll
llvm.amdgcn.buffer.wbinvl1.vol.ll
llvm.amdgcn.class.f16.ll
llvm.amdgcn.class.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.cos.f16.ll
llvm.amdgcn.cos.ll
llvm.amdgcn.cubeid.ll
llvm.amdgcn.cubema.ll
llvm.amdgcn.cubesc.ll
llvm.amdgcn.cubetc.ll
llvm.amdgcn.cvt.pk.i16.ll
llvm.amdgcn.cvt.pk.u16.ll
llvm.amdgcn.cvt.pknorm.i16.ll
llvm.amdgcn.cvt.pknorm.u16.ll
llvm.amdgcn.cvt.pkrtz.ll
llvm.amdgcn.dispatch.id.ll
llvm.amdgcn.dispatch.ptr.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
llvm.amdgcn.div.fixup.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.div.fixup.ll
llvm.amdgcn.div.fmas.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
llvm.amdgcn.div.scale.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.ds.bpermute.ll
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll
llvm.amdgcn.exp.compr.ll
llvm.amdgcn.exp.ll
llvm.amdgcn.fcmp.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fdot2.ll
llvm.amdgcn.fmad.ftz.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmad.ftz.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmed3.f16.ll
llvm.amdgcn.fmed3.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.fmul.legacy.ll
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll
llvm.amdgcn.frexp.exp.f16.ll
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll
llvm.amdgcn.icmp.ll
AMDGPU: Implement llvm.amdgcn.icmp/fcmp for i16/f16
2018-08-15 21:25:20 +00:00
llvm.amdgcn.image.a16.dim.ll
[AMDGPU] support image load/store a16
2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.atomic.dim.ll
llvm.amdgcn.image.d16.dim.ll
llvm.amdgcn.image.dim.ll
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] Add support for a16 modifiear for gfx9
2018-08-28 15:07:30 +00:00
llvm.amdgcn.image.gather4.d16.dim.ll
llvm.amdgcn.image.gather4.dim.ll
llvm.amdgcn.image.gather4.o.dim.ll
llvm.amdgcn.image.getlod.dim.ll
llvm.amdgcn.image.load.a16.d16.ll
[AMDGPU] support image load/store a16
2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.load.a16.ll
[AMDGPU] support image load/store a16
2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.sample.a16.dim.ll
[AMDGPU] Add support for a16 modifiear for gfx9
2018-08-28 15:07:30 +00:00
llvm.amdgcn.image.sample.d16.dim.ll
llvm.amdgcn.image.sample.dim.ll
llvm.amdgcn.image.sample.ltolz.ll
llvm.amdgcn.image.sample.o.dim.ll
llvm.amdgcn.image.store.a16.d16.ll
[AMDGPU] support image load/store a16
2018-10-31 10:34:48 +00:00
llvm.amdgcn.image.store.a16.ll
[AMDGPU] support image load/store a16
2018-10-31 10:34:48 +00:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
llvm.amdgcn.implicit.buffer.ptr.ll
llvm.amdgcn.implicitarg.ptr.ll
llvm.amdgcn.init.exec.ll
llvm.amdgcn.interp.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
llvm.amdgcn.kernarg.segment.ptr.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
llvm.amdgcn.kill.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.log.clamp.ll
llvm.amdgcn.mbcnt.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
llvm.amdgcn.mov.dpp.ll
llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.ps.live.ll
llvm.amdgcn.qsad.pk.u16.u8.ll
llvm.amdgcn.queue.ptr.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
llvm.amdgcn.raw.buffer.atomic.ll
AMDGPU: Future-proof {raw,struct}.buffer.atomic intrinsics
2018-10-08 16:53:48 +00:00
llvm.amdgcn.raw.buffer.load.format.d16.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.load.format.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.load.ll
[AMDGPU] Fix for negative offsets in buffer/tbuffer intrinsics
2018-10-03 10:29:43 +00:00
llvm.amdgcn.raw.buffer.store.format.d16.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.store.format.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU] Allow int types for MUBUF vdata
2018-08-21 11:08:12 +00:00
llvm.amdgcn.raw.tbuffer.load.d16.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.raw.tbuffer.store.d16.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.raw.tbuffer.store.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll
llvm.amdgcn.readfirstlane.ll
llvm.amdgcn.readlane.ll
llvm.amdgcn.rsq.clamp.ll
llvm.amdgcn.rsq.f16.ll
llvm.amdgcn.rsq.legacy.ll
llvm.amdgcn.rsq.ll
llvm.amdgcn.s.barrier.ll
llvm.amdgcn.s.dcache.inv.ll
llvm.amdgcn.s.dcache.inv.vol.ll
llvm.amdgcn.s.dcache.wb.ll
llvm.amdgcn.s.dcache.wb.vol.ll
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll
llvm.amdgcn.s.memtime.ll
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll
llvm.amdgcn.sad.hi.u8.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u8.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.sad.u16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.amdgcn.sbfe.ll
llvm.amdgcn.sdot2.ll
llvm.amdgcn.sdot4.ll
llvm.amdgcn.sdot8.ll
llvm.amdgcn.sendmsg.ll
llvm.amdgcn.set.inactive.ll
llvm.amdgcn.sffbh.ll
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll
llvm.amdgcn.struct.buffer.atomic.ll
AMDGPU: Future-proof {raw,struct}.buffer.atomic intrinsics
2018-10-08 16:53:48 +00:00
llvm.amdgcn.struct.buffer.load.format.d16.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.load.ll
[AMDGPU] Fix for negative offsets in buffer/tbuffer intrinsics
2018-10-03 10:29:43 +00:00
llvm.amdgcn.struct.buffer.store.format.d16.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.store.format.ll
[AMDGPU] New buffer intrinsics
2018-08-21 11:07:10 +00:00
llvm.amdgcn.struct.buffer.store.ll
[AMDGPU] Allow int types for MUBUF vdata
2018-08-21 11:08:12 +00:00
llvm.amdgcn.struct.tbuffer.load.d16.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.struct.tbuffer.store.d16.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.struct.tbuffer.store.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.tbuffer.load.d16.ll
llvm.amdgcn.tbuffer.load.ll
llvm.amdgcn.tbuffer.store.d16.ll
llvm.amdgcn.tbuffer.store.ll
[AMDGPU] New tbuffer intrinsics
2018-08-21 11:06:05 +00:00
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll
llvm.amdgcn.udot2.ll
llvm.amdgcn.udot4.ll
llvm.amdgcn.udot8.ll
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll
Relax fast register allocator related test cases; NFC
2018-10-29 20:10:42 +00:00
llvm.amdgcn.wave.barrier.ll
llvm.amdgcn.workgroup.id.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
llvm.amdgcn.workitem.id.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
llvm.amdgcn.wqm.vote.ll
llvm.amdgcn.writelane.ll
AMDGPU: Fix getInstSizeInBytes
2018-08-29 07:46:09 +00:00
llvm.AMDGPU.kill.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
llvm.ceil.f16.ll
llvm.cos.f16.ll
[AMDGPU] Ensure trig range reduction only used for subtargets that require it
2018-09-14 10:27:19 +00:00
llvm.cos.ll
llvm.dbg.value.ll
llvm.exp2.f16.ll
llvm.exp2.ll
llvm.floor.f16.ll
llvm.fma.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.fmuladd.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.log2.f16.ll
llvm.log2.ll
llvm.log10.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.log10.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.log.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.log.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
llvm.maxnum.f16.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
llvm.memcpy.ll
llvm.minnum.f16.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
llvm.pow.ll
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.f64.ll
llvm.round.ll
llvm.SI.load.dword.ll
llvm.SI.tbuffer.store.ll
llvm.sin.f16.ll
[AMDGPU] Ensure trig range reduction only used for subtargets that require it
2018-09-14 10:27:19 +00:00
llvm.sin.ll
[AMDGPU] Ensure trig range reduction only used for subtargets that require it
2018-09-14 10:27:19 +00:00
llvm.sqrt.f16.ll
llvm.trunc.f16.ll
load-constant-f32.ll
load-constant-f64.ll
load-constant-i1.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
load-constant-i8.ll
load-constant-i16.ll
load-constant-i32.ll
[AMDGPU] Split v32i32 loads
2018-08-31 22:43:36 +00:00
load-constant-i64.ll
load-global-f32.ll
load-global-f64.ll
load-global-i1.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
load-global-i8.ll
load-global-i16.ll
load-global-i32.ll
[AMDGPU] Split v32i32 loads
2018-08-31 22:43:36 +00:00
load-global-i64.ll
load-hi16.ll
load-input-fold.ll
load-lo16.ll
load-local-f32-no-ds128.ll
load-local-f32.ll
load-local-f64.ll
load-local-i1.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
load-local-i8.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
load-local-i16.ll
[SelectionDAG] Add FoldBUILD_VECTOR to simplify new BUILD_VECTOR nodes
2018-10-30 10:32:11 +00:00
load-local-i32.ll
[AMDGPU] Split v32i32 loads
2018-08-31 22:43:36 +00:00
load-local-i64.ll
load-select-ptr.ll
load-weird-sizes.ll
local-64.ll
local-atomics64.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
local-atomics.ll
[AMDGPU] Add an AMDGPU specific atomic optimizer.
2018-10-08 15:49:19 +00:00
local-memory.amdgcn.ll
local-memory.ll
local-memory.r600.ll
local-stack-slot-offset.ll
[AMDGPU] Remove FeatureVGPRSpilling
2018-10-31 18:54:06 +00:00
loop_break.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
loop_exit_with_xor.ll
loop-address.ll
loop-idiom.ll
lower-kernargs.ll
lower-mem-intrinsics.ll
lower-range-metadata-intrinsic-call.ll
lshl64-to-32.ll
lshr.v2i16.ll
macro-fusion-cluster-vcc-uses.mir
mad24-get-global-id.ll
mad_64_32.ll
mad_int24.ll
mad_uint24.ll
mad-combine.ll
mad-mix-hi.ll
AMDGPU: Remove custom BUILD_VECTOR combine
2018-10-30 01:37:59 +00:00
mad-mix-lo.ll
DAG: Handle odd vector sizes in calling conv splitting
2018-09-10 11:49:23 +00:00
mad-mix.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
madak-inline-constant.mir
[AMDGPU] Preliminary patch for divergence driven instruction selection. Inline immediate move to V_MADAK_F32.
2018-09-10 16:42:49 +00:00
madak.ll
madmk.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
max3.ll
max-literals.ll
max.i16.ll
max.ll
mem-builtins.ll
memory_clause.ll
memory_clause.mir
memory-legalizer-atomic-cmpxchg.ll
memory-legalizer-atomic-fence.ll
memory-legalizer-atomic-insert-end.mir
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
memory-legalizer-atomic-rmw.ll
memory-legalizer-invalid-addrspace.mir
memory-legalizer-invalid-syncscope.ll
memory-legalizer-load.ll
memory-legalizer-local.mir
memory-legalizer-multiple-mem-operands-atomics.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
memory-legalizer-region.mir
memory-legalizer-store-infinite-loop.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
memory-legalizer-store.ll
merge-load-store-physreg.mir
merge-load-store-vreg.mir
[AMDGPU] Fix ds combine with subregs
2018-09-25 23:33:18 +00:00
merge-load-store.mir
merge-m0.mir
merge-store-crash.ll
merge-store-usedef.ll
merge-stores.ll
mesa_regression.ll
min3.ll
min.ll
misched-killflags.mir
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
2018-10-30 15:04:40 +00:00
missing-store.ll
move-addr64-rsrc-dead-subreg-writes.ll
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll
movreld-bug.ll
movrels-bug.mir
mubuf-legalize-operands.ll
[AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions
2018-10-08 18:47:01 +00:00
mubuf-legalize-operands.mir
[AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions
2018-10-08 18:47:01 +00:00
mubuf-offset-private.ll
mubuf-shader-vgpr.ll
mubuf.ll
mul_int24.ll
mul_uint24-amdgcn.ll
mul_uint24-r600.ll
mul.i16.ll
mul.ll
multi-divergent-exit-region.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
multilevel-break.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
nested-calls.ll
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
2018-10-30 15:04:40 +00:00
nested-loop-conditions.ll
AMDGPU: Remove PHI loop condition optimization
2018-10-31 13:26:48 +00:00
no-hsa-graphics-shaders.ll
no-initializer-constant-addrspace.ll
no-shrink-extloads.ll
noop-shader-O0.ll
[AMDGPU] Remove FeatureVGPRSpilling
2018-10-31 18:54:06 +00:00
nop-data.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
not-scalarize-volatile-load.ll
nullptr.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
omod-nsz-flag.mir
omod.ll
opencl-image-metadata.ll
operand-folding.ll
operand-spacing.ll
opt-sgpr-to-vgpr-copy.mir
optimize-if-exec-masking.mir
AMDGPU: Fix some outdated datalayouts in tests
2018-09-13 11:56:28 +00:00
or.ll
over-max-lds-size.ll
pack.v2f16.ll
pack.v2i16.ll
packed-op-sel.ll
packetizer.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll
RegAllocFast: Leave unassigned virtreg entries in map
2018-11-07 06:57:03 +00:00
partial-shift-shrink.ll
partially-dead-super-register-immediate.ll
perfhint.ll
permute.ll
phi-elimination-assertion.mir
[PHIElimination] Lower a PHI node with only undef uses as IMPLICIT_DEF
2018-09-30 17:26:58 +00:00
pk_max_f16_literal.ll
postra-norename.mir
predicate-dp4.ll
predicates.ll
print-mir-custom-pseudo.ll
[AMDGPU] Rename pass "isel" to "amdgpu-isel"
2018-10-03 03:38:22 +00:00
private-access-no-objects.ll
private-element-size.ll
private-memory-atomics.ll
private-memory-r600.ll
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll
[AMDGPU] Add a pass to promote bitcast calls
2018-10-26 13:18:36 +00:00
promote-alloca-calling-conv.ll
promote-alloca-globals.ll
promote-alloca-invariant-markers.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
promote-alloca-lifetime.ll
promote-alloca-mem-intrinsics.ll
promote-alloca-no-opts.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
promote-alloca-padding-size-estimate.ll
Revert r345542: AMDGPU: Enable code object v3 by default
2018-10-30 22:02:40 +00:00
promote-alloca-stored-pointer-value.ll
promote-alloca-to-lds-icmp.ll
AMDGPU: Add an option -disable-promote-alloca-to-lds
2018-11-06 21:28:17 +00:00
promote-alloca-to-lds-phi.ll
promote-alloca-to-lds-select.ll
promote-alloca-unhandled-intrinsic.ll
promote-alloca-vector-to-vector.ll
[AMDGPU] Extend promote alloca vectorization
2018-11-08 00:16:23 +00:00
promote-alloca-volatile.ll
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.alu-limits.ll
r600.amdgpu-alias-analysis.ll
AMDGPU: Fix r600 test
2018-09-11 04:39:16 +00:00
r600.bitcast.ll
r600.extract-lowbits.ll
r600.func-alignment.ll
r600.global_atomics.ll
r600.private-memory.ll
r600.work-item-intrinsics.ll
r600cfg.ll
rcp_iflag.ll
rcp-pattern.ll
read_register.ll
read-register-invalid-subtarget.ll
read-register-invalid-type-i32.ll
read-register-invalid-type-i64.ll
readcyclecounter.ll
readlane_exec0.mir
README
reduce-build-vec-ext-to-ext-build-vec.ll
reduce-load-width-alignment.ll
reduce-saveexec.mir
reduce-store-width-alignment.ll
reduction.ll
DAG: Change behavior of fminnum/fmaxnum nodes
2018-10-22 16:27:27 +00:00
reg-coalescer-sched-crash.ll
regcoal-subrange-join-seg.mir
regcoal-subrange-join.mir
regcoalesce-dbg.mir
MachineOperand/MIParser: Do not print debug-use flag, infer it
2018-10-30 23:28:27 +00:00
regcoalesce-prune.mir
regcoalescing-remove-partial-redundancy-assert.mir
[RegisterCoalescer] Fix for assert in removePartialRedundancy
2018-08-23 17:28:33 +00:00
register-count-comments.ll
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir
rename-independent-subregs.mir
reorder-stores.ll
reqd-work-group-size.ll
ret_jump.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
ret.ll
rewrite-out-arguments-address-space.ll
rewrite-out-arguments.ll
rotl.i64.ll
rotl.ll
rotr.i64.ll
rotr.ll
rsq.ll
rv7x0_count3.ll
s_addk_i32.ll
s_movk_i32.ll
s_mulk_i32.ll
sad.ll
saddo.ll
salu-to-valu.ll
sampler-resource-id.ll
scalar_to_vector.ll
scalar-branch-missing-and-exec.ll
scalar-store-cache-flush.mir
sched-crash-dbg-value.mir
MachineOperand/MIParser: Do not print debug-use flag, infer it
2018-10-30 23:28:27 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll
schedule-if-2.ll
schedule-if.ll
schedule-ilp.ll
schedule-kernel-arg-loads.ll
schedule-regpressure-limit2.ll
schedule-regpressure-limit3.ll
schedule-regpressure-limit.ll
schedule-regpressure.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
schedule-vs-if-nested-loop-failure.ll
[AMDGPU] Remove FeatureVGPRSpilling
2018-10-31 18:54:06 +00:00
schedule-vs-if-nested-loop.ll
scheduler-subrange-crash.ll
scratch-buffer.ll
scratch-simple.ll
[AMDGPU] Remove FeatureVGPRSpilling
2018-10-31 18:54:06 +00:00
sdiv.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
sdivrem24.ll
sdivrem64.ll
sdwa-gfx9.mir
sdwa-peephole-instr.mir
sdwa-peephole.ll
sdwa-preserve.mir
sdwa-scalar-ops.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
sdwa-vop2-64bit.mir
select64.ll
select-fabs-fneg-extract-legacy.ll
select-fabs-fneg-extract.ll
select-i1.ll
select-opt.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
select-vectors.ll
select.f16.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
sendmsg-m0-hazard.mir
set-dx10.ll
setcc64.ll
setcc-equivalent.ll
setcc-fneg-constant.ll
setcc-limit-load-shrink.ll
Check shouldReduceLoadWidth from SimplifySetCC
2018-10-31 21:24:30 +00:00
setcc-opt.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
setcc-sext.ll
setcc.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
seto.ll
setuo.ll
sext-eliminate.ll
sext-in-reg-failure-r600.ll
sext-in-reg.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
sgpr-control-flow.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
sgpr-copy-duplicate-operand.ll
sgpr-copy.ll
sgpr-spill-wrong-stack-id.mir
sgprcopies.ll
shader-addr64-nonuniform.ll
shared-op-cycle.ll
shift-and-i64-ubfe.ll
shift-and-i128-ubfe.ll
shift-i64-opts.ll
shift-i128.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
shl_add_constant.ll
shl_add_ptr.ll
shl-add-to-add-shl.ll
shl.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
shl.v2i16.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
shrink-add-sub-constant.ll
shrink-carry.mir
shrink-vop3-carry-out.mir
si-annotate-cf-noloop.ll
si-annotate-cf-unreachable.ll
si-annotate-cf.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
si-annotate-cfg-loop-assert.ll
si-fix-sgpr-copies.mir
si-instr-info-correct-implicit-operands.ll
si-lower-control-flow-kill.ll
si-lower-control-flow-unreachable-block.ll
si-lower-control-flow.mir
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
si-scheduler.ll
si-sgpr-spill.ll
[AMDGPU] Remove FeatureVGPRSpilling
2018-10-31 18:54:06 +00:00
si-spill-cf.ll
si-spill-sgpr-stack.ll
si-triv-disjoint-mem-access.ll
si-vector-hang.ll
sibling-call.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
sign_extend.ll
simplify-libcalls.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
simplifydemandedbits-recursion.ll
sint_to_fp.f64.ll
sint_to_fp.i64.ll
sint_to_fp.ll
sitofp.f16.ll
[AMDGPU] Add instruction selection for i1 to f16 conversion
2018-09-19 16:32:12 +00:00
skip-if-dead.ll
smed3.ll
sminmax.ll
sminmax.v2i16.ll
smrd-fold-offset.mir
Revert "AMDGPU: Divergence-driven selection of scalar buffer load intrinsics"
2018-11-07 21:53:43 +00:00
smrd-vccz-bug.ll
smrd.ll
Revert "AMDGPU: Divergence-driven selection of scalar buffer load intrinsics"
2018-11-07 21:53:43 +00:00
sopk-compares.ll
spill-alloc-sgpr-init-bug.ll
spill-before-exec.mir
[RegAllocGreedy] avoid using physreg candidates that cannot be correctly spilled
2018-09-25 18:37:38 +00:00
spill-cfg-position.ll
spill-csr-frame-ptr-reg-copy.ll
spill-empty-live-interval.mir
spill-m0.ll
RegAllocFast: Leave unassigned virtreg entries in map
2018-11-07 06:57:03 +00:00
spill-offset-calculation.ll
spill-scavenge-offset.ll
spill-to-smem-m0.ll
spill-wide-sgpr.ll
Relax fast register allocator related test cases; NFC
2018-10-29 20:10:42 +00:00
split-scalar-i64-add.ll
CodeGen: Make computeRegisterLiveness consider successors
2018-08-30 07:17:51 +00:00
split-smrd.ll
split-vector-memoperand-offsets.ll
splitkit.mir
sra.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
srem.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
srl.ll
ssubo.ll
stack-realign.ll
stack-size-overflow.ll
stack-slot-color-sgpr-vgpr-spills.mir
store_typed.ll
store-barrier.ll
store-global.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
store-hi16.ll
store-local.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
store-private.ll
store-v3i64.ll
store-vector-ptrs.ll
store-weird-sizes.ll
stress-calls.ll
structurize1.ll
structurize.ll
sub_i1.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
sub.i16.ll
sub.ll
[AMDGPU] Divergence driven instruction selection. Part 1.
2018-09-21 10:31:22 +00:00
sub.v2i16.ll
[AMDGPU] Remove useless check from test. NFC.
2018-09-25 01:24:54 +00:00
subreg_interference.mir
subreg-coalescer-crash.ll
subreg-coalescer-undef-use.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
subreg-eliminate-dead.ll
subreg-intervals.mir
subreg-split-live-in-error.mir
swizzle-export.ll
syncscopes.ll
tail-call-cgp.ll
target-cpu.ll
tex-clause-antidep.ll
texture-input-merge.ll
trap.ll
trunc-bitcast-vector.ll
trunc-cmp-constant.ll
trunc-combine.ll
trunc-store-f64-to-f16.ll
trunc-store-i1.ll
trunc-store.ll
trunc-vector-store-assertion-failure.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
trunc.ll
tti-unroll-prefs.ll
twoaddr-mad.mir
uaddo.ll
udiv.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
udivrem24.ll
udivrem64.ll
udivrem.ll
uint_to_fp.f64.ll
uint_to_fp.i64.ll
uint_to_fp.ll
uitofp.f16.ll
[AMDGPU] Add instruction selection for i1 to f16 conversion
2018-09-19 16:32:12 +00:00
umed3.ll
unaligned-load-store.ll
DAG: Fix expansion of unaligned FP loads and stores
2018-09-13 12:14:23 +00:00
undefined-physreg-sgpr-spill.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
undefined-subreg-liverange.ll
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
2018-10-30 15:04:40 +00:00
unhandled-loop-condition-assertion.ll
uniform-branch-intrinsic-cond.ll
uniform-cfg.ll
uniform-crash.ll
uniform-loop-inside-nonuniform.ll
unify-metadata.ll
unigine-liveness-crash.ll
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
unknown-processor.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
unpack-half.ll
unroll.ll
unsupported-calls.ll
[AMDGPU] Add a pass to promote bitcast calls
2018-10-26 13:18:36 +00:00
unsupported-cc.ll
urem.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
use-sgpr-multiple-times.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
usubo.ll
v1i64-kernel-arg.ll
v_cndmask.ll
v_cvt_pk_u8_f32.ll
v_mac_f16.ll
v_mac.ll
v_madak_f16.ll
v_swap_b32.mir
[AMDGPU] Match v_swap_b32
2018-10-29 17:26:01 +00:00
valu-i1.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
vccz-corrupt-bug-workaround.mir
AMDGPU: Fix tests using old number for constant address space
2018-09-10 02:54:25 +00:00
vector-alloca-addrspacecast.ll
vector-alloca-atomic.ll
vector-alloca.ll
AMDGPU: Remove remnants of old address space mapping
2018-08-31 05:49:54 +00:00
vector-extract-insert.ll
vector-legalizer-divergence.ll
vectorize-global-local.ll
verifier-implicit-virtreg-invalid-physreg-liveness.mir
MachineVerifier: Fix assert on implicit virtreg use
2018-08-27 17:40:09 +00:00
vertex-fetch-encoding.ll
vgpr-spill-emergency-stack-slot-compute.ll
[AMDGPU] Remove FeatureVGPRSpilling
2018-10-31 18:54:06 +00:00
vgpr-spill-emergency-stack-slot.ll
[AMDGPU] Remove FeatureVGPRSpilling
2018-10-31 18:54:06 +00:00
vi-removed-intrinsics.ll
vop-shrink-frame-index.mir
vop-shrink-non-ssa.mir
vop-shrink.ll
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll
waitcnt-back-edge-loop.mir
waitcnt-debug.mir
waitcnt-flat.ll
waitcnt-loop-single-basic-block.mir
waitcnt-looptest.ll
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
2018-10-31 13:27:08 +00:00
waitcnt-no-redundant.mir
waitcnt-permute.mir
waitcnt.mir
wave_dispatch_regs.ll
widen_extending_scalar_loads.ll
widen-smrd-loads.ll
widen-vselect-and-mask.ll
wqm.ll
[AMDGPU] Preliminary patch for divergence driven instruction selection. Immediate selection predicate changed
2018-09-11 11:56:50 +00:00
wqm.mir
write_register.ll
write-register-vgpr-into-sgpr.ll
wrong-transalu-pos-fix.ll
xfail.r600.bitcast.ll
xnor.ll
xor.ll
zero_extend.ll
zext-i64-bit-operand.ll
zext-lid.ll
[SelectionDAG] Handle constant range [0,1) in lowerRangeToAssertZExt
2018-10-31 19:57:36 +00:00
