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https://github.com/RPCS3/llvm-mirror.git
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734b898f0d
Summary: Instead of writing boolean values temporarily into 32-bit VGPRs if they are involved in PHIs or are observed from outside a loop, we use bitwise masking operations to combine lane masks in a way that is consistent with wave control flow. Move SIFixSGPRCopies to before this pass, since that pass incorrectly attempts to move SGPR phis to VGPRs. This should recover most of the code quality that was lost with the bug fix in "AMDGPU: Remove PHI loop condition optimization". There are still some relevant cases where code quality could be improved, in particular: - We often introduce redundant masks with EXEC. Ideally, we'd have a generic computeKnownBits-like analysis to determine whether masks are already masked by EXEC, so we can avoid this masking both here and when lowering uniform control flow. - The criterion we use to determine whether a def is observed from outside a loop is conservative: it doesn't check whether (loop) branch conditions are uniform. Change-Id: Ibabdb373a7510e426b90deef00f5e16c5d56e64b Reviewers: arsenm, rampitec, tpr Subscribers: kzhuravl, jvesely, wdng, mgorny, yaxunl, dstuttard, t-tye, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D53496 llvm-svn: 345719
270 lines
7.6 KiB
LLVM
270 lines
7.6 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}inline_asm:
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; CHECK: s_endpgm
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; CHECK: s_endpgm
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define amdgpu_kernel void @inline_asm(i32 addrspace(1)* %out) {
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entry:
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store i32 5, i32 addrspace(1)* %out
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call void asm sideeffect "s_endpgm", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}inline_asm_shader:
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; CHECK: s_endpgm
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; CHECK: s_endpgm
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define amdgpu_ps void @inline_asm_shader() {
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entry:
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call void asm sideeffect "s_endpgm", ""()
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ret void
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}
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; CHECK: {{^}}branch_on_asm:
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; Make sure inline assembly is treted as divergent.
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; CHECK: s_mov_b32 s{{[0-9]+}}, 0
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; CHECK: s_and_saveexec_b64
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define amdgpu_kernel void @branch_on_asm(i32 addrspace(1)* %out) {
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%zero = call i32 asm "s_mov_b32 $0, 0", "=s"()
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%cmp = icmp eq i32 %zero, 0
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br i1 %cmp, label %if, label %endif
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if:
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store i32 0, i32 addrspace(1)* %out
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br label %endif
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endif:
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ret void
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}
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; CHECK-LABEL: {{^}}v_cmp_asm:
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; CHECK: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
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; CHECK: v_cmp_ne_u32_e64 s{{\[}}[[MASK_LO:[0-9]+]]:[[MASK_HI:[0-9]+]]{{\]}}, 0, [[SRC]]
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; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[MASK_LO]]
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; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[MASK_HI]]
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; CHECK: buffer_store_dwordx2 v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
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define amdgpu_kernel void @v_cmp_asm(i64 addrspace(1)* %out, i32 %in) {
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%sgpr = tail call i64 asm "v_cmp_ne_u32_e64 $0, 0, $1", "=s,v"(i32 %in)
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store i64 %sgpr, i64 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm:
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; CHECK: codeLenInByte = 12
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define amdgpu_kernel void @code_size_inline_asm(i32 addrspace(1)* %out) {
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entry:
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call void asm sideeffect "v_nop_e64", ""()
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ret void
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}
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; All inlineasm instructions are assumed to be the maximum size
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; CHECK-LABEL: {{^}}code_size_inline_asm_small_inst:
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; CHECK: codeLenInByte = 12
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define amdgpu_kernel void @code_size_inline_asm_small_inst(i32 addrspace(1)* %out) {
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entry:
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call void asm sideeffect "v_nop_e32", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst:
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; CHECK: codeLenInByte = 20
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define amdgpu_kernel void @code_size_inline_asm_2_inst(i32 addrspace(1)* %out) {
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entry:
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call void asm sideeffect "
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v_nop_e64
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v_nop_e64
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", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst_extra_newline:
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; CHECK: codeLenInByte = 20
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define amdgpu_kernel void @code_size_inline_asm_2_inst_extra_newline(i32 addrspace(1)* %out) {
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entry:
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call void asm sideeffect "
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v_nop_e64
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v_nop_e64
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", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_0_inst:
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; CHECK: codeLenInByte = 4
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define amdgpu_kernel void @code_size_inline_asm_0_inst(i32 addrspace(1)* %out) {
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entry:
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call void asm sideeffect "", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment:
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; CHECK: codeLenInByte = 4
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define amdgpu_kernel void @code_size_inline_asm_1_comment(i32 addrspace(1)* %out) {
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entry:
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call void asm sideeffect "; comment", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_newline_1_comment:
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; CHECK: codeLenInByte = 4
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define amdgpu_kernel void @code_size_inline_asm_newline_1_comment(i32 addrspace(1)* %out) {
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entry:
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call void asm sideeffect "
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; comment", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment_newline:
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; CHECK: codeLenInByte = 4
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define amdgpu_kernel void @code_size_inline_asm_1_comment_newline(i32 addrspace(1)* %out) {
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entry:
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call void asm sideeffect "; comment
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", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line:
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; CHECK: codeLenInByte = 4
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define amdgpu_kernel void @code_size_inline_asm_2_comments_line(i32 addrspace(1)* %out) {
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entry:
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call void asm sideeffect "; first comment ; second comment", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line_nospace:
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; CHECK: codeLenInByte = 4
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define amdgpu_kernel void @code_size_inline_asm_2_comments_line_nospace(i32 addrspace(1)* %out) {
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entry:
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call void asm sideeffect "; first comment;second comment", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments0:
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; CHECK: codeLenInByte = 20
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define amdgpu_kernel void @code_size_inline_asm_mixed_comments0(i32 addrspace(1)* %out) {
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entry:
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call void asm sideeffect "; comment
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v_nop_e64 ; inline comment
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; separate comment
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v_nop_e64
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; trailing comment
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; extra comment
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", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments1:
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; CHECK: codeLenInByte = 20
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define amdgpu_kernel void @code_size_inline_asm_mixed_comments1(i32 addrspace(1)* %out) {
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entry:
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call void asm sideeffect "v_nop_e64 ; inline comment
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; separate comment
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v_nop_e64
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; trailing comment
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; extra comment
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", ""()
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ret void
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}
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; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments_operands:
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; CHECK: codeLenInByte = 20
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define amdgpu_kernel void @code_size_inline_asm_mixed_comments_operands(i32 addrspace(1)* %out) {
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entry:
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call void asm sideeffect "; comment
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v_add_i32_e32 v0, vcc, v1, v2 ; inline comment
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; separate comment
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v_bfrev_b32_e32 v0, 1
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; trailing comment
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; extra comment
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", ""()
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ret void
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}
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; FIXME: Should not have intermediate sgprs
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; CHECK-LABEL: {{^}}i64_imm_input_phys_vgpr:
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; CHECK-DAG: s_mov_b32 s1, 0
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; CHECK-DAG: s_mov_b32 s0, 0x1e240
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; CHECK: v_mov_b32_e32 v0, s0
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; CHECK: v_mov_b32_e32 v1, s1
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; CHECK: use v[0:1]
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define amdgpu_kernel void @i64_imm_input_phys_vgpr() {
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entry:
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call void asm sideeffect "; use $0 ", "{v[0:1]}"(i64 123456)
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ret void
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}
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; CHECK-LABEL: {{^}}i1_imm_input_phys_vgpr:
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; CHECK: s_mov_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], -1
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, [[MASK]]
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; CHECK: ; use v0
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define amdgpu_kernel void @i1_imm_input_phys_vgpr() {
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entry:
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call void asm sideeffect "; use $0 ", "{v0}"(i1 true)
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ret void
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}
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; CHECK-LABEL: {{^}}i1_input_phys_vgpr:
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; CHECK: {{buffer|flat}}_load_ubyte [[LOAD:v[0-9]+]]
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; CHECK: v_and_b32_e32 [[LOAD]], 1, [[LOAD]]
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 1, [[LOAD]]
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
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; CHECK: ; use v0
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; CHECK: v_cmp_ne_u32_e32 vcc, 0, v1
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; CHECK: v_cndmask_b32_e64 [[STORE:v[0-9]+]], 0, 1, vcc
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; CHECK: {{buffer|flat}}_store_byte [[STORE]],
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define amdgpu_kernel void @i1_input_phys_vgpr() {
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entry:
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%val = load i1, i1 addrspace(1)* undef
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%cc = call i1 asm sideeffect "; use $1, def $0 ", "={v1}, {v0}"(i1 %val)
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store i1 %cc, i1 addrspace(1)* undef
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ret void
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}
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; FIXME: Should be scheduled to shrink vcc
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; CHECK-LABEL: {{^}}i1_input_phys_vgpr_x2:
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; CHECK: v_cmp_eq_u32_e32 vcc, 1, v0
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; CHECK: v_cndmask_b32_e64 v0, 0, -1, vcc
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; CHECK: v_cmp_eq_u32_e32 vcc, 1, v1
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; CHECK: v_cndmask_b32_e64 v1, 0, -1, vcc
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define amdgpu_kernel void @i1_input_phys_vgpr_x2() {
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entry:
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%val0 = load volatile i1, i1 addrspace(1)* undef
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%val1 = load volatile i1, i1 addrspace(1)* undef
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call void asm sideeffect "; use $0 $1 ", "{v0}, {v1}"(i1 %val0, i1 %val1)
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ret void
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}
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; CHECK-LABEL: {{^}}muliple_def_phys_vgpr:
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; CHECK: ; def v0
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; CHECK: v_mov_b32_e32 v1, v0
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; CHECK: ; def v0
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; CHECK: v_lshlrev_b32_e32 v{{[0-9]+}}, v0, v1
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define amdgpu_kernel void @muliple_def_phys_vgpr() {
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entry:
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%def0 = call i32 asm sideeffect "; def $0 ", "={v0}"()
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%def1 = call i32 asm sideeffect "; def $0 ", "={v0}"()
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%add = shl i32 %def0, %def1
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store i32 %add, i32 addrspace(1)* undef
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ret void
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}
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; CHECK-LABEL: {{^}}asm_constraint_c_n:
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; CHECK: s_trap 10{{$}}
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define amdgpu_kernel void @asm_constraint_c_n() {
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entry:
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tail call void asm sideeffect "s_trap ${0:c}", "n"(i32 10) #1
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ret void
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}
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; CHECK-LABEL: {{^}}asm_constraint_n_n:
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; CHECK: s_trap -10{{$}}
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define amdgpu_kernel void @asm_constraint_n_n() {
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entry:
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tail call void asm sideeffect "s_trap ${0:n}", "n"(i32 10) #1
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ret void
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}
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