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5f7023b12c
llvm-mirror/lib/Target/AArch64
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Ahmed Bougacha 5f7023b12c [AArch64] Support selecting STNP. 
We could go through the load/store optimizer and match STNP where
we would have matched a nontemporal-annotated STP, but that's not
reliable enough, as an opportunistic optimization.
Insetad, we can guarantee emitting STNP, by matching them at ISel.
Since there are no single-input nontemporal stores, we have to
resort to some high-bits-extracting trickery to generate an STNP
from a plain store.

Also, we need to support another, LDP/STP-specific addressing mode,
base + signed scaled 7-bit immediate offset.
For now, only match the base. Let's make it smart separately.

Part of PR24086.

llvm-svn: 247231
2015-09-10 01:42:28 +00:00
..
AsmParser [AArch64] Improve short-form diags on long-form Match_InvalidOperand. 2015-08-19 17:40:19 +00:00
Disassembler
InstPrinter
MCTargetDesc MC: Remove MCSubtargetInfo() default constructor 2015-07-10 22:43:42 +00:00
TargetInfo
Utils [AArch64][v8.1a] The "pan" sysreg isn't MSR-specific. NFCI. 2015-08-04 00:55:11 +00:00
AArch64.h
AArch64.td [AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0. 2015-09-01 16:23:45 +00:00
AArch64A53Fix835769.cpp Fix some comment typos. 2015-08-08 18:27:36 +00:00
AArch64A57FPLoadBalancing.cpp MachineRegisterInfo: Remove UsedPhysReg infrastructure 2015-07-14 17:52:07 +00:00
AArch64AddressTypePromotion.cpp [AArch64] Make the naming of the Address Type Promotion pass consistent. 2015-08-05 15:32:23 +00:00
AArch64AdvSIMDScalarPass.cpp [AArch64] Register (existing) AArch64AdvSIMDScalar pass with LLVM pass manager. 2015-08-05 15:18:58 +00:00
AArch64AsmPrinter.cpp
AArch64BranchRelaxation.cpp [AArch64] Register (existing) AArch64BranchRelaxation pass with LLVM pass manager. 2015-08-05 16:12:10 +00:00
AArch64CallingConvention.h Move most user of TargetMachine::getDataLayout to the Module one 2015-07-16 06:11:10 +00:00
AArch64CallingConvention.td Move most user of TargetMachine::getDataLayout to the Module one 2015-07-16 06:11:10 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp [AArch64][CollectLOH] Remove an invalid assertion and add a test case exposing it. 2015-08-31 19:02:00 +00:00
AArch64ConditionalCompares.cpp wrap OptSize and MinSize attributes for easier and consistent access (NFCI) 2015-08-04 15:49:57 +00:00
AArch64ConditionOptimizer.cpp AArch64: use AddressingModes.h accessors for compare shifts 2015-07-29 16:39:56 +00:00
AArch64DeadRegisterDefinitionsPass.cpp [AArch64] Register AArch64DeadRegisterDefinition pass with LLVM pass manager. 2015-08-05 17:35:34 +00:00
AArch64ExpandPseudoInsts.cpp [AArch64] Register (existing) AArch64ExpandPseudo pass with LLVM pass manager. 2015-08-05 14:22:53 +00:00
AArch64FastISel.cpp FastISel: Factor out common code; NFC intended 2015-08-26 01:38:00 +00:00
AArch64FrameLowering.cpp Remove redundant TargetFrameLowering::getFrameIndexOffset virtual 2015-08-15 02:32:35 +00:00
AArch64FrameLowering.h Remove redundant TargetFrameLowering::getFrameIndexOffset virtual 2015-08-15 02:32:35 +00:00
AArch64InstrAtomics.td
AArch64InstrFormats.td [AArch64] Support selecting STNP. 2015-09-10 01:42:28 +00:00
AArch64InstrInfo.cpp [MIR Serialization] static -> static const in getSerializable*MachineOperandTargetFlags 2015-08-30 08:07:29 +00:00
AArch64InstrInfo.h MIR Serialization: Serialize the operand's bit mask target flags. 2015-08-18 22:52:15 +00:00
AArch64InstrInfo.td [AArch64] Support selecting STNP. 2015-09-10 01:42:28 +00:00
AArch64ISelDAGToDAG.cpp [AArch64] Support selecting STNP. 2015-09-10 01:42:28 +00:00
AArch64ISelLowering.cpp Remove white space (test commit) 2015-09-08 16:11:22 +00:00
AArch64ISelLowering.h [AArch64] Replace the custom AArch64ISD::FMIN/MAX nodes with ISD::FMINNAN/MAXNAN 2015-08-11 12:06:33 +00:00
AArch64LoadStoreOptimizer.cpp Revert "[AArch64] Improve load/store optimizer to handle LDUR + LDR." 2015-09-03 16:41:28 +00:00
AArch64MachineCombinerPattern.h
AArch64MachineFunctionInfo.h Fix typo "fuction" noticed in comments in AssumptionCache.h, and also all the other files that have the same typo. All comments, no functionality change! (Merely a "fuctionality" change.) 2015-07-29 22:32:47 +00:00
AArch64MCInstLower.cpp Convert some AArch64 code to foreach loops. NFC. 2015-08-03 19:04:32 +00:00
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp Rename inst_range() to instructions() for consistency. NFC 2015-08-06 19:10:45 +00:00
AArch64RegisterInfo.cpp [AArch64] Remove check for Darwin that was needed to decide if x18 should 2015-07-27 19:18:47 +00:00
AArch64RegisterInfo.h Targets: commonize some stack realignment code 2015-07-20 22:51:32 +00:00
AArch64RegisterInfo.td
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp Remove getDataLayout() from TargetSelectionDAGInfo (had no users) 2015-07-09 02:10:08 +00:00
AArch64SelectionDAGInfo.h Remove getDataLayout() from TargetSelectionDAGInfo (had no users) 2015-07-09 02:10:08 +00:00
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp [AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0. 2015-09-01 16:23:45 +00:00
AArch64Subtarget.h [AArch64] Lower READCYCLECOUNTER using MRS PMCCTNR_EL0. 2015-09-01 16:23:45 +00:00
AArch64TargetMachine.cpp
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp [CostModel][AArch64] Remove amortization factor for some of the vector select instructions 2015-09-09 15:35:02 +00:00
AArch64TargetTransformInfo.h [AArch64] Turn on by default interleaved access vectorization 2015-09-01 11:26:46 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile