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e23fa40f7f
An encoding does not allow to use SDWA in an instruction with scalar operands, either literals or SGPRs. That is however possible to copy these operands into a VGPR first. Several copies of the value are produced if multiple SDWA conversions were done. To cleanup MachineLICM (to hoist copies out of loops), MachineCSE (to remove duplicate copies) and SIFoldOperands (to replace SGPR to VGPR copy with immediate copy right to the VGPR) runs are added after the SDWA pass. Differential Revision: https://reviews.llvm.org/D33583 llvm-svn: 304219
102 lines
3.3 KiB
LLVM
102 lines
3.3 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
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; DAGCombiner will transform:
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; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
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; unless isFabsFree returns true
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; FUNC-LABEL: {{^}}fabs_fn_free:
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; R600-NOT: AND
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; R600: |PV.{{[XYZW]}}|
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; GCN: v_and_b32
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define amdgpu_kernel void @fabs_fn_free(float addrspace(1)* %out, i32 %in) {
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%bc= bitcast i32 %in to float
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%fabs = call float @fabs(float %bc)
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store float %fabs, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_free:
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; R600-NOT: AND
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; R600: |PV.{{[XYZW]}}|
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; GCN: v_and_b32
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define amdgpu_kernel void @fabs_free(float addrspace(1)* %out, i32 %in) {
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%bc= bitcast i32 %in to float
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%fabs = call float @llvm.fabs.f32(float %bc)
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store float %fabs, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_f32:
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; GCN: v_and_b32
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define amdgpu_kernel void @fabs_f32(float addrspace(1)* %out, float %in) {
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%fabs = call float @llvm.fabs.f32(float %in)
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store float %fabs, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_v2f32:
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; GCN: v_and_b32
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; GCN: v_and_b32
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define amdgpu_kernel void @fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
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store <2 x float> %fabs, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_v4f32:
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; GCN: v_and_b32
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; GCN: v_and_b32
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; GCN: v_and_b32
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; GCN: v_and_b32
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define amdgpu_kernel void @fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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%fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
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store <4 x float> %fabs, <4 x float> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fabs_fn_fold:
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; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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; VI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
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; GCN-NOT: and
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; GCN: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
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define amdgpu_kernel void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) {
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%fabs = call float @fabs(float %in0)
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%fmul = fmul float %fabs, %in1
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store float %fmul, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fabs_fold:
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; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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; VI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
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; GCN-NOT: and
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; GCN: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
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define amdgpu_kernel void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) {
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%fabs = call float @llvm.fabs.f32(float %in0)
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%fmul = fmul float %fabs, %in1
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store float %fmul, float addrspace(1)* %out
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ret void
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}
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declare float @fabs(float) readnone
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declare float @llvm.fabs.f32(float) readnone
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declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
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declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
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