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e48d05bbd3
This change modifies the LLVM ISel lowering settings so that 8-bit/16-bit multiplication is expanded to calls into the compiler runtime library if the MCU being targeted does not support multiplication in hardware. Before this, MUL instructions would be generated on CPUs like the ATtiny85, triggering a CPU reset due to an illegal instruction at runtime. First raised in https://github.com/avr-rust/rust/issues/124. llvm-svn: 351523
31 lines
668 B
LLVM
31 lines
668 B
LLVM
; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s
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; Tests lowering of multiplication to hardware instructions.
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define i8 @mult8(i8 %a, i8 %b) {
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; CHECK-LABEL: mult8:
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; CHECK: muls r22, r24
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; CHECK: clr r1
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; CHECK: mov r24, r0
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%mul = mul i8 %b, %a
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ret i8 %mul
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}
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define i16 @mult16(i16 %a, i16 %b) {
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; CHECK-LABEL: mult16:
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; CHECK: muls r22, r25
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; CHECK: mov r18, r0
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; CHECK: mul r22, r24
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; CHECK: mov r19, r0
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; CHECK: mov r20, r1
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; CHECK: clr r1
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; CHECK: add r20, r18
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; CHECK: muls r23, r24
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; CHECK: clr r1
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; CHECK: mov r22, r0
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; CHECK: add r22, r20
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; :TODO: finish after reworking shift instructions
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%mul = mul nsw i16 %b, %a
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ret i16 %mul
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}
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