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llvm-mirror/test/CodeGen/AVR/hardware-mul.ll

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[AVR] Add a selection of CodeGen tests Summary: This adds all of the CodeGen tests which currently pass. Reviewers: arsenm, kparzysz Subscribers: japaric, wdng Differential Revision: https://reviews.llvm.org/D26388 llvm-svn: 286418
2016-11-10 00:46:52 +01:00
; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s
[AVR] Expand 8/16-bit multiplication to libcalls on MCUs that don't have hardware MUL This change modifies the LLVM ISel lowering settings so that 8-bit/16-bit multiplication is expanded to calls into the compiler runtime library if the MCU being targeted does not support multiplication in hardware. Before this, MUL instructions would be generated on CPUs like the ATtiny85, triggering a CPU reset due to an illegal instruction at runtime. First raised in https://github.com/avr-rust/rust/issues/124. llvm-svn: 351523
2019-01-18 07:10:41 +01:00
; Tests lowering of multiplication to hardware instructions.
[AVR] Add a selection of CodeGen tests Summary: This adds all of the CodeGen tests which currently pass. Reviewers: arsenm, kparzysz Subscribers: japaric, wdng Differential Revision: https://reviews.llvm.org/D26388 llvm-svn: 286418
2016-11-10 00:46:52 +01:00
define i8 @mult8(i8 %a, i8 %b) {
; CHECK-LABEL: mult8:
; CHECK: muls r22, r24
[AVR] Use the short form of 'clr <reg>' r318895 made it so that the simpler instruction aliases are printed rather than their expanded form. llvm-svn: 318954
2017-11-24 16:36:43 +01:00
; CHECK: clr r1
[AVR] Add a selection of CodeGen tests Summary: This adds all of the CodeGen tests which currently pass. Reviewers: arsenm, kparzysz Subscribers: japaric, wdng Differential Revision: https://reviews.llvm.org/D26388 llvm-svn: 286418
2016-11-10 00:46:52 +01:00
; CHECK: mov r24, r0
%mul = mul i8 %b, %a
ret i8 %mul
}
define i16 @mult16(i16 %a, i16 %b) {
; CHECK-LABEL: mult16:
; CHECK: muls r22, r25
; CHECK: mov r18, r0
; CHECK: mul r22, r24
; CHECK: mov r19, r0
; CHECK: mov r20, r1
[AVR] Use the short form of 'clr <reg>' r318895 made it so that the simpler instruction aliases are printed rather than their expanded form. llvm-svn: 318954
2017-11-24 16:36:43 +01:00
; CHECK: clr r1
[AVR] Add a selection of CodeGen tests Summary: This adds all of the CodeGen tests which currently pass. Reviewers: arsenm, kparzysz Subscribers: japaric, wdng Differential Revision: https://reviews.llvm.org/D26388 llvm-svn: 286418
2016-11-10 00:46:52 +01:00
; CHECK: add r20, r18
; CHECK: muls r23, r24
[AVR] Use the short form of 'clr <reg>' r318895 made it so that the simpler instruction aliases are printed rather than their expanded form. llvm-svn: 318954
2017-11-24 16:36:43 +01:00
; CHECK: clr r1
[AVR] Add a selection of CodeGen tests Summary: This adds all of the CodeGen tests which currently pass. Reviewers: arsenm, kparzysz Subscribers: japaric, wdng Differential Revision: https://reviews.llvm.org/D26388 llvm-svn: 286418
2016-11-10 00:46:52 +01:00
; CHECK: mov r22, r0
; CHECK: add r22, r20
; :TODO: finish after reworking shift instructions
%mul = mul nsw i16 %b, %a
ret i16 %mul
}
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