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0e3bafc4e2
Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
115 lines
4.4 KiB
LLVM
115 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f,+d < %s | FileCheck %s
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; Check the GHC call convention works (rv32)
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@base = external global i32 ; assigned to register: s1
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@sp = external global i32 ; assigned to register: s2
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@hp = external global i32 ; assigned to register: s3
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@r1 = external global i32 ; assigned to register: s4
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@r2 = external global i32 ; assigned to register: s5
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@r3 = external global i32 ; assigned to register: s6
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@r4 = external global i32 ; assigned to register: s7
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@r5 = external global i32 ; assigned to register: s8
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@r6 = external global i32 ; assigned to register: s9
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@r7 = external global i32 ; assigned to register: s10
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@splim = external global i32 ; assigned to register: s11
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@f1 = external global float ; assigned to register: fs0
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@f2 = external global float ; assigned to register: fs1
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@f3 = external global float ; assigned to register: fs2
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@f4 = external global float ; assigned to register: fs3
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@f5 = external global float ; assigned to register: fs4
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@f6 = external global float ; assigned to register: fs5
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@d1 = external global double ; assigned to register: fs6
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@d2 = external global double ; assigned to register: fs7
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@d3 = external global double ; assigned to register: fs8
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@d4 = external global double ; assigned to register: fs9
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@d5 = external global double ; assigned to register: fs10
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@d6 = external global double ; assigned to register: fs11
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define ghccc void @foo() nounwind {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a0, %hi(d6)
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; CHECK-NEXT: fld fs11, %lo(d6)(a0)
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; CHECK-NEXT: lui a0, %hi(d5)
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; CHECK-NEXT: fld fs10, %lo(d5)(a0)
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; CHECK-NEXT: lui a0, %hi(d4)
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; CHECK-NEXT: fld fs9, %lo(d4)(a0)
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; CHECK-NEXT: lui a0, %hi(d3)
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; CHECK-NEXT: fld fs8, %lo(d3)(a0)
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; CHECK-NEXT: lui a0, %hi(d2)
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; CHECK-NEXT: fld fs7, %lo(d2)(a0)
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; CHECK-NEXT: lui a0, %hi(d1)
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; CHECK-NEXT: fld fs6, %lo(d1)(a0)
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; CHECK-NEXT: lui a0, %hi(f6)
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; CHECK-NEXT: flw fs5, %lo(f6)(a0)
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; CHECK-NEXT: lui a0, %hi(f5)
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; CHECK-NEXT: flw fs4, %lo(f5)(a0)
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; CHECK-NEXT: lui a0, %hi(f4)
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; CHECK-NEXT: flw fs3, %lo(f4)(a0)
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; CHECK-NEXT: lui a0, %hi(f3)
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; CHECK-NEXT: flw fs2, %lo(f3)(a0)
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; CHECK-NEXT: lui a0, %hi(f2)
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; CHECK-NEXT: flw fs1, %lo(f2)(a0)
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; CHECK-NEXT: lui a0, %hi(f1)
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; CHECK-NEXT: flw fs0, %lo(f1)(a0)
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; CHECK-NEXT: lui a0, %hi(splim)
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; CHECK-NEXT: lw s11, %lo(splim)(a0)
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; CHECK-NEXT: lui a0, %hi(r7)
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; CHECK-NEXT: lw s10, %lo(r7)(a0)
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; CHECK-NEXT: lui a0, %hi(r6)
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; CHECK-NEXT: lw s9, %lo(r6)(a0)
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; CHECK-NEXT: lui a0, %hi(r5)
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; CHECK-NEXT: lw s8, %lo(r5)(a0)
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; CHECK-NEXT: lui a0, %hi(r4)
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; CHECK-NEXT: lw s7, %lo(r4)(a0)
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; CHECK-NEXT: lui a0, %hi(r3)
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; CHECK-NEXT: lw s6, %lo(r3)(a0)
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; CHECK-NEXT: lui a0, %hi(r2)
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; CHECK-NEXT: lw s5, %lo(r2)(a0)
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; CHECK-NEXT: lui a0, %hi(r1)
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; CHECK-NEXT: lw s4, %lo(r1)(a0)
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; CHECK-NEXT: lui a0, %hi(hp)
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; CHECK-NEXT: lw s3, %lo(hp)(a0)
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; CHECK-NEXT: lui a0, %hi(sp)
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; CHECK-NEXT: lw s2, %lo(sp)(a0)
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; CHECK-NEXT: lui a0, %hi(base)
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; CHECK-NEXT: lw s1, %lo(base)(a0)
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; CHECK-NEXT: tail bar@plt
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entry:
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%0 = load double, double* @d6
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%1 = load double, double* @d5
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%2 = load double, double* @d4
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%3 = load double, double* @d3
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%4 = load double, double* @d2
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%5 = load double, double* @d1
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%6 = load float, float* @f6
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%7 = load float, float* @f5
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%8 = load float, float* @f4
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%9 = load float, float* @f3
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%10 = load float, float* @f2
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%11 = load float, float* @f1
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%12 = load i32, i32* @splim
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%13 = load i32, i32* @r7
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%14 = load i32, i32* @r6
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%15 = load i32, i32* @r5
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%16 = load i32, i32* @r4
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%17 = load i32, i32* @r3
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%18 = load i32, i32* @r2
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%19 = load i32, i32* @r1
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%20 = load i32, i32* @hp
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%21 = load i32, i32* @sp
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%22 = load i32, i32* @base
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tail call ghccc void @bar(i32 %22, i32 %21, i32 %20, i32 %19, i32 %18, i32 %17, i32 %16, i32 %15, i32 %14, i32 %13, i32 %12,
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float %11, float %10, float %9, float %8, float %7, float %6,
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double %5, double %4, double %3, double %2, double %1, double %0) nounwind
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ret void
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}
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declare ghccc void @bar(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
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float, float, float, float, float, float,
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double, double, double, double, double, double)
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