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d6c9e38a37
In vector v0.10, there are whole vector register load/store
instructions. I suggest to use the whole register load/store
instructions for generic load/store for scalable vector types. It could
save up vset{i}vl{i} for these load/store.
For fractional LMUL, I keep to use vle{eew}.v/vse{eew}.v instructions to
load/store partial vector registers.
Differential Revision: https://reviews.llvm.org/D95853
25 lines
924 B
LLVM
25 lines
924 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
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; This demonstrates that we can pass a struct containing scalable vectors across
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; a basic block.
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define i32 @foo({ {<vscale x 2 x i32>, <vscale x 2 x i32>}, i32 } %x, <vscale x 2 x i32>* %y, <vscale x 2 x i32>* %z) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vs1r.v v8, (a1)
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; CHECK-NEXT: vs1r.v v9, (a2)
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; CHECK-NEXT: ret
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entry:
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br label %return
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return:
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%a = extractvalue { {<vscale x 2 x i32>, <vscale x 2 x i32>}, i32 } %x, 1
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%b = extractvalue { {<vscale x 2 x i32>, <vscale x 2 x i32>}, i32 } %x, 0, 0
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%c = extractvalue { {<vscale x 2 x i32>, <vscale x 2 x i32>}, i32 } %x, 0, 1
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store <vscale x 2 x i32> %b, <vscale x 2 x i32>* %y
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store <vscale x 2 x i32> %c, <vscale x 2 x i32>* %z
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ret i32 %a
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}
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