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llvm-mirror/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

32 lines
1.1 KiB
YAML

# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
--- |
define void @addrspace_memoperands() {
ret void
}
...
---
name: addrspace_memoperands
body: |
bb.0:
; CHECK-LABEL: name: addrspace_memoperands
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8, addrspace 1)
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4, align 2, addrspace 3)
; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store 8, addrspace 1)
; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store 4, align 2, addrspace 3)
; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store 4)
; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s64) = G_LOAD %0(p0) :: (load 8, addrspace 1)
%2:_(s32) = G_LOAD %0(p0) :: (load 4, align 2, addrspace 3)
G_STORE %1(s64), %0(p0) :: (store 8, addrspace 1)
G_STORE %2(s32), %0(p0) :: (store 4, align 2, addrspace 3)
; addrspace 0 is accepted by the parser but not printed
G_STORE %2(s32), %0(p0) :: (store 4, addrspace 0)
RET_ReallyLR
...