Craig Topper 6d7c1c4298 [RISCV] Don't use tail agnostic policy on instructions where destination is tied to source ... If the destination is tied, then user has some control of the register used for input. They would have the ability to control the value of any tail elements. By using tail agnostic we take this option away from them. Its not clear that the intrinsics are defined such that this isn't supposed to work. And undisturbed is a valid implementation for agnostic so code wouldn't even fail to work on all systems if we always used agnostic. The vcompress intrinsic is defined to require tail undisturbed so at minimum we need this for that instruction or need to redefine the intrinsic. I've made an exception here for vmv.s.x/fmv.s.f and reduction instructions which only write to element 0 regardless of the tail policy. This allows us to keep the agnostic policy on those which should allow better redundant vsetvli removal. An enhancement would be to check for undef input and keep the agnostic policy, but we don't have good test coverage for that yet. Reviewed By: khchen Differential Revision: https://reviews.llvm.org/D93878		2020-12-29 10:37:58 -08:00
..
AsmParser	[RISCV] Improve VMConstraint checking on more unary and nullary instructions.	2020-12-26 18:47:59 -08:00
Disassembler	[RISCV] Support Zfh half-precision floating-point extension.	2020-12-03 09:16:33 +08:00
MCTargetDesc	[RISCV] Move vtype decoding and printing from RISCVInstPrinter to RISCVBaseInfo. Share with the assembly parser's debug output	2020-12-14 10:50:26 -08:00
TargetInfo	llvmbuildectomy - replace llvm-build by plain cmake	2020-11-13 10:35:24 +01:00
Utils	[RISCV] Don't use tail agnostic policy on instructions where destination is tied to source	2020-12-29 10:37:58 -08:00
CMakeLists.txt	[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.	2020-12-11 10:35:37 -08:00
RISCV.h	[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.	2020-12-11 10:35:37 -08:00
RISCV.td	[RISCV] V does not imply F.	2020-12-17 10:57:36 +08:00
RISCVAsmPrinter.cpp	[RISCV] Add -mtune support	2020-10-16 13:55:08 +08:00
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVCleanupVSETVLI.cpp	[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.	2020-12-11 10:35:37 -08:00
RISCVExpandAtomicPseudoInsts.cpp	[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos	2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp	[RISCV] Define vmclr.m/vmset.m intrinsics.	2020-12-28 18:57:17 -08:00
RISCVFrameLowering.cpp	[RISCV] Support Zfh half-precision floating-point extension.	2020-12-03 09:16:33 +08:00
RISCVFrameLowering.h	[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.	2020-11-05 11:02:18 +00:00
RISCVInstrFormats.td	[RISCV] Improve VMConstraint checking on more unary and nullary instructions.	2020-12-26 18:47:59 -08:00
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td	[RISCV] add the MC layer support of riscv vector Zvamo extension	2020-08-27 14:11:38 +08:00
RISCVInstrInfo.cpp	[Target] Use llvm::erase_if (NFC)	2020-12-20 17:43:22 -08:00
RISCVInstrInfo.h	[RISCV] Don't include CodeGen layer files in MC layer	2020-11-12 07:45:38 -08:00
RISCVInstrInfo.td	[RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions	2020-12-10 19:25:51 +00:00
RISCVInstrInfoA.td	RISCV: Avoid GlobalISel build break in a future patch	2020-07-13 14:01:57 -04:00
RISCVInstrInfoB.td	[RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions	2020-12-10 19:25:51 +00:00
RISCVInstrInfoC.td	[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump	2020-12-04 10:34:12 -08:00
RISCVInstrInfoD.td	[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.	2020-12-10 09:15:52 -08:00
RISCVInstrInfoF.td	[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.	2020-12-10 09:15:52 -08:00
RISCVInstrInfoM.td	[RISCV] Don't remove (and X, 0xffffffff) from inputs when matching RISCVISD::DIVUW/REMUW to 64-bit DIVU/REMU.	2020-11-26 23:15:41 -08:00
RISCVInstrInfoV.td	[RISCV] Improve VMConstraint checking on more unary and nullary instructions.	2020-12-26 18:47:59 -08:00
RISCVInstrInfoVPseudos.td	[RISCV] Don't use tail agnostic policy on instructions where destination is tied to source	2020-12-29 10:37:58 -08:00
RISCVInstrInfoVSDPatterns.td	[RISCV] Add ISel support for RVV vector/scalar forms	2020-12-23 20:16:18 +00:00
RISCVInstrInfoZfh.td	[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.	2020-12-10 09:15:52 -08:00
RISCVInstructionSelector.cpp	RISCV: Avoid GlobalISel build break in a future patch	2020-07-13 14:01:57 -04:00
RISCVISelDAGToDAG.cpp	[RISCV] Pattern-match more vector-splatted constants	2020-12-28 07:11:10 +00:00
RISCVISelDAGToDAG.h	[RISCV] Add ISel support for RVV vector/scalar forms	2020-12-23 20:16:18 +00:00
RISCVISelLowering.cpp	[RISCV] Don't use tail agnostic policy on instructions where destination is tied to source	2020-12-29 10:37:58 -08:00
RISCVISelLowering.h	[RISCV] Add ISel support for RVV vector/scalar forms	2020-12-23 20:16:18 +00:00
RISCVLegalizerInfo.cpp
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h	[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align	2020-07-01 07:28:11 +00:00
RISCVMCInstLower.cpp	[RISCV] Basic jump table lowering	2020-12-22 15:05:54 +00:00
RISCVMergeBaseOffset.cpp	[RISCV] Support Zfh half-precision floating-point extension.	2020-12-03 09:16:33 +08:00
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp	[RISCV] Define the remaining vector fixed-point arithmetic intrinsics.	2020-12-20 22:57:07 -08:00
RISCVRegisterInfo.h	CodeGen: More conversions to use Register	2020-04-07 18:54:36 -04:00
RISCVRegisterInfo.td	[RISCV] Define the remaining vector fixed-point arithmetic intrinsics.	2020-12-20 22:57:07 -08:00
RISCVSchedRocket.td	[RISCV] Fix formatting (NFC)	2020-09-25 18:15:04 -05:00
RISCVSchedSiFive7.td	[RISCV] Use the commercial name for scheduling model (NFC)	2020-10-23 16:33:27 -05:00
RISCVSchedule.td	[RISCV] Fix formatting (NFC)	2020-09-25 18:15:04 -05:00
RISCVSubtarget.cpp	[RISCV] Add -mtune support	2020-10-16 13:55:08 +08:00
RISCVSubtarget.h	[RISCV] Support Zfh half-precision floating-point extension.	2020-12-03 09:16:33 +08:00
RISCVSystemOperands.td	[RISCV] Enable the use of the old mucounteren name	2020-08-17 13:11:49 +01:00
RISCVTargetMachine.cpp	[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.	2020-12-18 21:50:55 +00:00
RISCVTargetMachine.h	[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.	2020-12-18 21:50:55 +00:00
RISCVTargetObjectFile.cpp	[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.	2020-05-21 15:23:29 -07:00
RISCVTargetObjectFile.h	[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.	2020-05-21 15:23:29 -07:00
RISCVTargetTransformInfo.cpp	[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop	2020-09-22 11:54:10 +00:00
RISCVTargetTransformInfo.h	[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop	2020-09-22 11:54:10 +00:00