Chad Rosier 0b83599b15 [AArch64] Fix an assertion for pre-index generation with unscaled loads/stores. ... Differential Revision: https://reviews.llvm.org/D36248 PR34035 llvm-svn: 310066		2017-08-04 16:44:06 +00:00
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AArch64	[AArch64] Fix an assertion for pre-index generation with unscaled loads/stores.	2017-08-04 16:44:06 +00:00
AMDGPU	[AMDGPU] Preserve inverted bit in SI_IF in presence of SI_KILL	2017-08-04 06:58:42 +00:00
ARM	Revert r309923, it caused PR34045.	2017-08-03 15:41:26 +00:00
AVR	[AVR] Remove the instrumentation pass	2017-07-23 23:39:11 +00:00
BPF	DAG: Undo and->or combine with FrameIndexes	2017-08-02 00:43:42 +00:00
Generic	[TargetPassConfig] Feature generic options to setup start/stop-after/before	2017-07-31 18:24:07 +00:00
Hexagon	[Hexagon] Convert HVX vector constants of i1 to i8	2017-08-01 13:12:53 +00:00
Inputs
Lanai
Mips	[mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SP	2017-08-04 10:18:44 +00:00
MIR	[MIR] Print target-specific constant pools	2017-08-02 11:09:30 +00:00
MSP430
Nios2
NVPTX
PowerPC	[Power9] Exploit vector absolute difference instructions on Power 9	2017-08-02 20:07:21 +00:00
SPARC
SystemZ	[SystemZ] test update	2017-07-21 13:14:17 +00:00
Thumb
Thumb2	ARM: Do not use llc -march in tests.	2017-08-01 22:20:49 +00:00
WebAssembly
WinEH
X86	[DAGCombiner] Extending pattern detection for vector shuffle.	2017-08-04 12:46:35 +00:00
XCore	Delete Default and JITDefault code models	2017-08-03 02:16:21 +00:00