Nicolai Haehnle 730a184595 AMDGPU/SI: Fix regression with no-return atomics ... Summary: In the added test-case, the atomic instruction feeds into a non-machine CopyToReg node which hasn't been selected yet, so guard against non-machine opcodes here. Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19043 llvm-svn: 266433		2016-04-15 14:42:36 +00:00
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AArch64	AArch64: expand cmpxchg after regalloc at -O0.	2016-04-14 17:03:29 +00:00
AMDGPU	AMDGPU/SI: Fix regression with no-return atomics	2016-04-15 14:42:36 +00:00
ARM	[CodeGen] Teach LLVM how to lower @llvm.{min,max}num to {MIN,MAX}NAN	2016-04-14 07:13:24 +00:00
BPF
CPP
Generic
Hexagon	Revert r265817	2016-04-08 18:15:37 +00:00
Inputs
Lanai	[lanai] Add custom lowering for SRL_PARTS i32.	2016-04-14 17:59:22 +00:00
Mips	Summary:	2016-04-14 13:43:17 +00:00
MIR	CodeGen: Clear the MFI's save and restore point after PrologEpilogInserter	2016-04-12 23:21:53 +00:00
MSP430
NVPTX	Move divergent-target test into CodeGen/NVPTX because it requires an NVPTX target.	2016-04-15 01:20:52 +00:00
PowerPC	[ppc] add tests to show potential andc optimization	2016-04-13 23:23:30 +00:00
SPARC
SystemZ	[SystemZ] Support conditional indirect sibling calls via BCR	2016-04-11 12:12:32 +00:00
Thumb	Revert r265817	2016-04-08 18:15:37 +00:00
Thumb2	ARM: use r7 as the frame-pointer on all MachO targets.	2016-04-11 22:27:40 +00:00
WebAssembly	[WebAssembly] Fix debug info in reg-stackify.ll test	2016-04-12 20:12:05 +00:00
WinEH
X86	Revert "Support arbitrary addrspace pointers in masked load/store intrinsics"	2016-04-14 08:47:17 +00:00
XCore