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History

Kai Luo bb3575b0df [PowerPC][Peephole] Check if extsw's second operand is a virtual register

Summary:
When combining `extsw` and `sldi` in `PPCMIPeephole`, we have to check
if `extsw`'s second operand is a virtual register, otherwise we might
get miscompile.

Differential Revision: https://reviews.llvm.org/D65315

llvm-svn: 367645

2019-08-02 03:14:17 +00:00

AArch64

Rename ExpandISelPseudo->FinalizeISel, delay register reservation

2019-06-19 00:25:39 +00:00

AMDGPU

AMDGPU/LoadStoreOptimizer: combine MMOs when merging instructions

2019-07-29 16:40:58 +00:00

ARM

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Generic

Rename ExpandISelPseudo->FinalizeISel, delay register reservation

2019-06-19 00:25:39 +00:00

Hexagon

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Mips

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

NVPTX

[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.

2018-01-10 00:56:48 +00:00

PowerPC

[PowerPC][Peephole] Check if extsw's second operand is a virtual register

2019-08-02 03:14:17 +00:00

WebAssembly

[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)

2018-05-08 02:02:50 +00:00

X86

[MachineFunction] Base support for call site info tracking

2019-06-27 07:48:06 +00:00

README

Add README describing the intention of test/CodeGen/MIR

2016-12-09 20:16:12 +00:00

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.