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4bf7d5872e
Upgrade of the IR text tests should be the only thing blocking making typed byval mandatory. Partially done through regex and partially manual.
62 lines
2.5 KiB
LLVM
62 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv7-unknown-linux < %s -stop-before=finalize-isel | FileCheck --check-prefix=BEFORE-EXPAND %s
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; RUN: llc -mtriple=armv7-unknown-linux < %s | FileCheck --check-prefix=ASSEMBLY %s
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; Check COPY_STRUCT_BYVAL_I32 has CPSR as operand.
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; BEFORE-EXPAND: COPY_STRUCT_BYVAL_I32 {{.*}} implicit-def dead $cpsr
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; BEFORE-EXPAND: COPY_STRUCT_BYVAL_I32 {{.*}} implicit-def dead $cpsr
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%struct.anon = type { i32, i32, i32, i32, i32, i32, i32, %struct.f, i32, i64, i32 }
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%struct.f = type { i32, i32, i32, i32, i32 }
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define arm_aapcscc void @s(i64* %q, %struct.anon* %p) {
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; ASSEMBLY-LABEL: s:
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; ASSEMBLY: @ %bb.0: @ %entry
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; ASSEMBLY-NEXT: push {r4, r5, r11, lr}
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; ASSEMBLY-NEXT: sub sp, sp, #136
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; ASSEMBLY-NEXT: ldrd r4, r5, [r0]
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; ASSEMBLY-NEXT: add lr, sp, #56
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; ASSEMBLY-NEXT: ldm r1, {r0, r12}
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; ASSEMBLY-NEXT: subs r4, r4, #1
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; ASSEMBLY-NEXT: sbc r5, r5, #0
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; ASSEMBLY-NEXT: ldr r2, [r1, #8]
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; ASSEMBLY-NEXT: ldr r3, [r1, #12]
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; ASSEMBLY-NEXT: str r5, [sp, #132]
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; ASSEMBLY-NEXT: add r5, r1, #16
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; ASSEMBLY-NEXT: str r4, [sp, #128]
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; ASSEMBLY-NEXT: mov r4, sp
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; ASSEMBLY-NEXT: vld1.32 {d16}, [r5]!
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; ASSEMBLY-NEXT: vst1.32 {d16}, [r4]!
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; ASSEMBLY-NEXT: vld1.32 {d16}, [r5]!
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; ASSEMBLY-NEXT: vst1.32 {d16}, [r4]!
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; ASSEMBLY-NEXT: vld1.32 {d16}, [r5]!
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; ASSEMBLY-NEXT: vst1.32 {d16}, [r4]!
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; ASSEMBLY-NEXT: vld1.32 {d16}, [r5]!
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; ASSEMBLY-NEXT: vst1.32 {d16}, [r4]!
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; ASSEMBLY-NEXT: vld1.32 {d16}, [r5]!
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; ASSEMBLY-NEXT: vst1.32 {d16}, [r4]!
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; ASSEMBLY-NEXT: vld1.32 {d16}, [r5]!
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; ASSEMBLY-NEXT: vst1.32 {d16}, [r4]!
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; ASSEMBLY-NEXT: vld1.32 {d16}, [r5]!
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; ASSEMBLY-NEXT: vst1.32 {d16}, [r4]!
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; ASSEMBLY-NEXT: movw r4, #72
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; ASSEMBLY-NEXT: .LBB0_1: @ %entry
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; ASSEMBLY-NEXT: @ =>This Inner Loop Header: Depth=1
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; ASSEMBLY-NEXT: vld1.32 {d16}, [r1]!
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; ASSEMBLY-NEXT: subs r4, r4, #8
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; ASSEMBLY-NEXT: vst1.32 {d16}, [lr]!
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; ASSEMBLY-NEXT: bne .LBB0_1
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; ASSEMBLY-NEXT: @ %bb.2: @ %entry
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; ASSEMBLY-NEXT: mov r1, r12
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; ASSEMBLY-NEXT: bl r
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; ASSEMBLY-NEXT: add sp, sp, #136
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; ASSEMBLY-NEXT: pop {r4, r5, r11, pc}
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entry:
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%0 = load i64, i64* %q, align 8
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%sub = add nsw i64 %0, -1
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tail call arm_aapcscc void bitcast (void (...)* @r to void (%struct.anon*, %struct.anon*, i64)*)(%struct.anon* byval(%struct.anon) nonnull align 8 %p, %struct.anon* byval(%struct.anon) nonnull align 8 %p, i64 %sub)
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ret void
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}
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declare arm_aapcscc void @r(...)
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