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llvm-mirror/test/CodeGen
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Evgeniy Stepanov 71027a56d5 Fix llvm.aarch64.irg properties. 
Summary:
IRG does not access any memory.
Replace IntrInaccessibleMemOnly with IntrNoMem | IntrHasSideEffects.

Reviewers: chill

Subscribers: javed.absar, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64447

llvm-svn: 368362
2019-08-08 22:42:48 +00:00
..
AArch64
Fix llvm.aarch64.irg properties.
2019-08-08 22:42:48 +00:00
AMDGPU
[MBP] Disable aggressive loop rotate in plain mode
2019-08-08 20:25:23 +00:00
ARC
…
ARM
[MBP] Disable aggressive loop rotate in plain mode
2019-08-08 20:25:23 +00:00
AVR
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BPF
[Transforms] Do not drop !preserve.access.index metadata
2019-08-03 23:41:26 +00:00
Generic
…
Hexagon
[MBP] Disable aggressive loop rotate in plain mode
2019-08-08 20:25:23 +00:00
Inputs
[CodeGen] Add stack protector tests where the guard gets re-assigned
2019-07-17 20:46:16 +00:00
Lanai
[SDAG] commute setcc operands to match a subtract
2019-07-10 23:23:54 +00:00
Mips
[MIPS GlobalISel] Select jump_table and brjt
2019-08-08 10:21:12 +00:00
MIR
[PowerPC][Peephole] Check if extsw's second operand is a virtual register
2019-08-02 03:14:17 +00:00
MSP430
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NVPTX
[NVPTX] Fix PR41651
2019-07-30 19:52:01 +00:00
PowerPC
[MBP] Disable aggressive loop rotate in plain mode
2019-08-08 20:25:23 +00:00
RISCV
[MBP] Disable aggressive loop rotate in plain mode
2019-08-08 20:25:23 +00:00
SPARC
…
SystemZ
[SystemZ] Regenerate <8 x i31> store test
2019-07-29 09:49:23 +00:00
Thumb
[MBP] Disable aggressive loop rotate in plain mode
2019-08-08 20:25:23 +00:00
Thumb2
[ARM] Add support for MVE pre and post inc loads and stores
2019-08-08 15:27:58 +00:00
WebAssembly
[TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::EXTRACT_VECTOR_ELT
2019-08-08 10:37:03 +00:00
WinCFGuard
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WinEH
IR: print value numbers for unnamed function arguments
2019-08-03 14:28:34 +00:00
X86
[X86] Improve codegen of v8i64->v8i16 and v16i32->v16i8 truncate with avx512vl, avx512bw, min-legal-vector-width<=256 and prefer-vector-width=256
2019-08-08 21:36:47 +00:00
XCore
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