ShihPo Hung 694d055478 [RISCV] Implement COPY for Zvlsseg registers ... When copying Zvlsseg register tuples, we split the COPY to NF whole register moves as below: $v10m2_v12m2 = COPY $v4m2_v6m2 # NF = 2 => $v10m2 = PseudoVMV2R_V $v4m2 $v12m2 = PseudoVMV2R_V $v6m2 This patch copies forwardCopyWillClobberTuple from AArch64 to check register overlapping. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D100280		2021-04-13 18:55:51 -07:00
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AsmParser	Title: [RISCV] Add missing part of instruction vmsge {u}. VX Review By: craig.topper Differential Revision : https://reviews.llvm.org/D100115	2021-04-14 06:41:59 +08:00
Disassembler
MCTargetDesc	[RISCV] Improve 64-bit integer constant materialization for more cases.	2021-04-02 10:18:08 -07:00
TargetInfo
CMakeLists.txt
RISCV.h	[RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'	2021-03-16 10:02:35 -07:00
RISCV.td	[RISCV][NFC] Fix formatting	2021-04-09 14:41:09 +08:00
RISCVAsmPrinter.cpp	[RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'	2021-03-16 10:02:35 -07:00
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVCleanupVSETVLI.cpp	[RISCV] Optimize more redundant VSETVLIs	2021-04-02 10:04:07 +01:00
RISCVExpandAtomicPseudoInsts.cpp
RISCVExpandPseudoInsts.cpp	[RISCV] Spilling for Zvlsseg registers.	2021-03-19 07:46:16 +08:00
RISCVFrameLowering.cpp	[NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions	2021-03-30 17:31:39 +01:00
RISCVFrameLowering.h	[RISCV] Fix offset computation for RVV	2021-03-29 17:03:49 +00:00
RISCVInstrFormats.td
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td
RISCVInstrInfo.cpp	[RISCV] Implement COPY for Zvlsseg registers	2021-04-13 18:55:51 -07:00
RISCVInstrInfo.h	[RISCV] Spilling for Zvlsseg registers.	2021-03-19 07:46:16 +08:00
RISCVInstrInfo.td	[RISCV] Add a generic PatGprImm class and use it to simplify patterns in RISCVInstrInfoB.td. NFC	2021-04-13 12:07:24 -07:00
RISCVInstrInfoA.td	[RISCV][NFC] Add explicit type i64 to RV64 only patterns.	2021-04-09 09:37:04 +08:00
RISCVInstrInfoB.td	[RISCV] Add a generic PatGprImm class and use it to simplify patterns in RISCVInstrInfoB.td. NFC	2021-04-13 12:07:24 -07:00
RISCVInstrInfoC.td	[RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg.	2021-03-19 20:39:49 -07:00
RISCVInstrInfoD.td	[RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC	2021-03-26 16:37:20 -07:00
RISCVInstrInfoF.td	[RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC	2021-03-26 16:37:20 -07:00
RISCVInstrInfoM.td	[RISCV] Add custom type legalization to form MULHSU when possible.	2021-04-01 10:15:55 -07:00
RISCVInstrInfoV.td	Title: [RISCV] Add missing part of instruction vmsge {u}. VX Review By: craig.topper Differential Revision : https://reviews.llvm.org/D100115	2021-04-14 06:41:59 +08:00
RISCVInstrInfoVPseudos.td	[RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf.	2021-04-11 10:19:45 -07:00
RISCVInstrInfoVSDPatterns.td	[RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates	2021-04-12 18:36:45 +01:00
RISCVInstrInfoVVLPatterns.td	[RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates	2021-04-12 18:36:45 +01:00
RISCVInstrInfoZfh.td	[RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC	2021-03-26 16:37:20 -07:00
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp	[RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates	2021-04-12 18:36:45 +01:00
RISCVISelDAGToDAG.h	[RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates	2021-04-12 18:36:45 +01:00
RISCVISelLowering.cpp	[RISCV] Rename RISCVISD::GREVI(W)/GORCI(W) to RISCVISD::GREV(W)/GORC(W). Don't require second operand to be a constant.	2021-04-13 11:04:28 -07:00
RISCVISelLowering.h	[RISCV] Rename RISCVISD::GREVI(W)/GORCI(W) to RISCVISD::GREV(W)/GORC(W). Don't require second operand to be a constant.	2021-04-13 11:04:28 -07:00
RISCVLegalizerInfo.cpp
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h	[RISCV] Fix offset computation for RVV	2021-03-29 17:03:49 +00:00
RISCVMCInstLower.cpp	[RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'	2021-03-16 10:02:35 -07:00
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp	[RISCV] Add scalable offset under very large stack size.	2021-04-08 14:46:05 +08:00
RISCVRegisterInfo.h
RISCVRegisterInfo.td	[RISCV] Support inline asm for vector instructions.	2021-03-15 11:02:18 +08:00
RISCVSchedRocket.td	[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC	2021-03-31 15:06:14 -07:00
RISCVSchedSiFive7.td	[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC	2021-03-31 15:06:14 -07:00
RISCVSchedule.td	[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC	2021-03-31 15:06:14 -07:00
RISCVScheduleB.td	[RISCV] Move scheduling resources for B into a separate file (NFC)	2021-03-29 20:37:22 -05:00
RISCVSubtarget.cpp	[RISCV] Give an explicit error if 'generic' CPU is passed instead of 'generic-rv32' or 'generic-rv64'. Validate 64Bit feature against the triple.	2021-03-14 17:21:31 -07:00
RISCVSubtarget.h
RISCVSystemOperands.td
RISCVTargetMachine.cpp
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp	[TTI] NFC: Change getGatherScatterOpCost to return InstructionCost	2021-04-13 14:20:59 +01:00
RISCVTargetTransformInfo.h	[TTI] NFC: Change getGatherScatterOpCost to return InstructionCost	2021-04-13 14:20:59 +01:00