Krzysztof Parzyszek 790c43253d Add test/CodeGen/MIR/Hexagon/lit.local.cfg ... Require that Hexagon is a registered target. llvm-svn: 270887		2016-05-26 18:35:45 +00:00
..
AArch64	[AArch64] Generate a BFI/BFXIL from 'or (and X, MaskImm), OrImm'.	2016-05-26 13:27:56 +00:00
AMDGPU	[AMDGPU] Remove exit-on-error flag from test (PR27762)	2016-05-26 15:24:55 +00:00
ARM	[ARM, AArch64] Match additional patterns to ldN instructions	2016-05-19 21:39:00 +00:00
BPF	[BPF] Remove exit-on-error flag in test (PR27767)	2016-05-26 15:23:50 +00:00
Generic
Hexagon	When looking for a spill slot in reg scavenger, find one that matches RC	2016-05-18 18:16:00 +00:00
Inputs
Lanai	[lanai] Change reloc to use PIC_ by default and cleanup.	2016-05-20 21:41:53 +00:00
Mips	[mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine verifier.	2016-05-19 10:42:14 +00:00
MIR	Add test/CodeGen/MIR/Hexagon/lit.local.cfg	2016-05-26 18:35:45 +00:00
MSP430
NVPTX	[NVPTX] Added NVVMIntrRange pass	2016-05-26 17:02:56 +00:00
PowerPC	Move and add comments to the top for tailcall-string-rvo.ll	2016-05-25 17:01:09 +00:00
SPARC	[SPARC] Fix 8 and 16-bit atomic load and store.	2016-05-23 20:33:00 +00:00
SystemZ	[SystemZ] Fix register ordering for BinaryRRF instructions	2016-05-18 13:24:57 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Put __stack_pointer in the offset field of loads and stores.	2016-05-24 23:47:41 +00:00
WinEH
X86	[X86][SSE] When lowering a 256-bit shuffle as PMOVZX, reduce the input vector to the lower 128-bit subvector.	2016-05-26 15:40:36 +00:00
XCore