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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 10:42:39 +01:00
llvm-mirror/lib/Target/Hexagon
Benjamin Kramer 7a0b21ccae [Hexagon] Silence warning
llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp:296:11: warning: enumeration value 'ScalableVectorTyID' not handled in switch [-Wswitch]
  switch (Ty->getTypeID()) {
          ^
2020-04-22 18:57:08 +02:00
..
AsmParser [MCStreamer] De-capitalize EmitValue EmitIntValue{,InHex} 2020-02-14 23:08:40 -08:00
Disassembler [Hexagon] v67+ HVX register pairs should support either direction 2020-02-14 12:43:43 -06:00
MCTargetDesc [MC][Bugfix] Remove redundant parameter for relaxInstruction 2020-04-21 11:06:55 +08:00
TargetInfo CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
BitTracker.cpp
BitTracker.h
CMakeLists.txt Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
Hexagon.h
Hexagon.td [TableGen] Support combining AssemblerPredicates with ORs 2020-03-13 17:13:51 +00:00
HexagonArch.h [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonAsmPrinter.cpp [MCStreamer] De-capitalize EmitValue EmitIntValue{,InHex} 2020-02-14 23:08:40 -08:00
HexagonAsmPrinter.h [AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI* 2020-02-13 22:08:55 -08:00
HexagonBitSimplify.cpp [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonBitTracker.cpp [Alignment][NFC] Transition to MachineFrameInfo::getObjectAlign() 2020-04-01 14:08:28 +00:00
HexagonBitTracker.h
HexagonBlockRanges.cpp
HexagonBlockRanges.h
HexagonBranchRelaxation.cpp [Alignment][NFC] Deprecate Align::None() 2020-01-24 12:53:58 +01:00
HexagonCallingConv.td
HexagonCFGOptimizer.cpp
HexagonCommonGEP.cpp Remove SequentialType from the type heirarchy. 2020-04-06 17:03:49 -07:00
HexagonConstExtenders.cpp [Hexagon] Add a target feature to disable compound instructions 2020-01-16 12:37:30 -06:00
HexagonConstPropagation.cpp [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonCopyToCombine.cpp [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonDepArch.h [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonDepArch.td [TableGen] Support combining AssemblerPredicates with ORs 2020-03-13 17:13:51 +00:00
HexagonDepDecoders.inc [Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm 2020-01-23 09:38:54 -06:00
HexagonDepIICHVX.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepIICScalar.td [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonDepInstrFormats.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepInstrInfo.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepITypes.h [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepITypes.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepMapAsm2Intrin.td [Hexagon] Map dcfetch intrinsic to Y2_dcfetchbo, not Y2_dcfetch 2020-02-28 14:19:20 -06:00
HexagonDepMappings.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepMask.h [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonDepOperands.td [Hexagon] Remove unused operand definitions: s10_0Imm and s10_6Imm 2020-01-23 09:38:54 -06:00
HexagonDepTimingClasses.h [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonEarlyIfConv.cpp
HexagonExpandCondsets.cpp
HexagonFixupHwLoops.cpp [Alignment][NFC] Deprecate Align::None() 2020-01-24 12:53:58 +01:00
HexagonFrameLowering.cpp CodeGen: Use Register in TargetFrameLowering 2020-04-07 17:07:44 -04:00
HexagonFrameLowering.h CodeGen: Use Register in TargetFrameLowering 2020-04-07 17:07:44 -04:00
HexagonGenExtract.cpp
HexagonGenInsert.cpp
HexagonGenMux.cpp
HexagonGenPredicate.cpp
HexagonHardwareLoops.cpp CodeGen: Convert some TII hooks to use Register 2020-04-03 14:52:54 -04:00
HexagonHazardRecognizer.cpp
HexagonHazardRecognizer.h
HexagonIICHVX.td
HexagonIICScalar.td
HexagonInstrFormats.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonInstrFormatsV60.td
HexagonInstrFormatsV65.td
HexagonInstrInfo.cpp CodeGen: Convert some TII hooks to use Register 2020-04-03 14:52:54 -04:00
HexagonInstrInfo.h CodeGen: Convert some TII hooks to use Register 2020-04-03 14:52:54 -04:00
HexagonIntrinsics.td [Hexagon] Map dcfetch intrinsic to Y2_dcfetchbo, not Y2_dcfetch 2020-02-28 14:19:20 -06:00
HexagonIntrinsicsV5.td
HexagonIntrinsicsV60.td [Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1 2020-02-19 14:14:56 -06:00
HexagonISelDAGToDAG.cpp [Alignment][NFC] Deprecate getMaxAlignment 2020-03-18 14:48:45 +01:00
HexagonISelDAGToDAG.h [AsmPrinter] De-capitalize Emit{Function,BasicBlock]* and Emit{Start,End}OfAsmFile 2020-02-13 13:22:49 -08:00
HexagonISelDAGToDAGHVX.cpp [Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1 2020-02-19 14:14:56 -06:00
HexagonISelLowering.cpp [CallSite removal][TargetLowering] Replace ImmutableCallSite with CallBase 2020-04-13 13:50:15 -07:00
HexagonISelLowering.h CodeGen: Use Register in TargetLowering 2020-04-08 12:10:58 -04:00
HexagonISelLoweringHVX.cpp [Hexagon] Only allow single HVX vector loads/stores in lowering 2020-03-14 14:26:01 -05:00
HexagonLoopIdiomRecognition.cpp
HexagonMachineFunctionInfo.cpp
HexagonMachineFunctionInfo.h Add support for Linux/Musl ABI 2020-01-20 09:59:56 -06:00
HexagonMachineScheduler.cpp
HexagonMachineScheduler.h
HexagonMapAsm2IntrinV62.gen.td
HexagonMapAsm2IntrinV65.gen.td
HexagonMCInstLower.cpp [Hexagon][NFC] Rename VK_Hexagon_PCREL to VK_PCREL 2020-02-19 09:52:58 -06:00
HexagonNewValueJump.cpp
HexagonOperands.td
HexagonOptAddrMode.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
HexagonOptimizeSZextends.cpp
HexagonPatterns.td [Hexagon] Fix fshl/fshr -> combine() bug identified in D75114 2020-03-06 17:23:10 +00:00
HexagonPatternsHVX.td
HexagonPatternsV65.td
HexagonPeephole.cpp
HexagonPseudo.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonRDFOpt.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
HexagonRegisterInfo.cpp CodeGen: Use Register in TargetFrameLowering 2020-04-07 17:07:44 -04:00
HexagonRegisterInfo.h [TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true 2020-01-19 14:20:37 -08:00
HexagonRegisterInfo.td [Hexagon] Change HVX vector predicate types from v512/1024i1 to v64/128i1 2020-02-19 14:14:56 -06:00
HexagonSchedule.td [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonScheduleV5.td
HexagonScheduleV55.td
HexagonScheduleV60.td
HexagonScheduleV62.td
HexagonScheduleV65.td
HexagonScheduleV66.td
HexagonScheduleV67.td [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonScheduleV67T.td [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
HexagonSelectionDAGInfo.cpp
HexagonSelectionDAGInfo.h
HexagonSplitConst32AndConst64.cpp
HexagonSplitDouble.cpp CodeGen: Convert some TII hooks to use Register 2020-04-03 14:52:54 -04:00
HexagonStoreWidening.cpp [Alignment][NFC] Use Align version of getMachineMemOperand 2020-03-30 15:46:27 +00:00
HexagonSubtarget.cpp Provide operand indices to adjustSchedDependency 2020-04-17 11:08:44 +01:00
HexagonSubtarget.h Provide operand indices to adjustSchedDependency 2020-04-17 11:08:44 +01:00
HexagonTargetMachine.cpp [Hexagon] Add support for Hexagon/HVX v67 ISA 2020-01-20 16:16:49 -06:00
HexagonTargetMachine.h
HexagonTargetObjectFile.cpp [Hexagon] Silence warning 2020-04-22 18:57:08 +02:00
HexagonTargetObjectFile.h
HexagonTargetStreamer.h [MC] De-capitalize another set of MCStreamer::Emit* functions 2020-02-14 19:26:52 -08:00
HexagonTargetTransformInfo.cpp [SVE] Remove calls to getBitWidth from Hexagon 2020-04-14 11:09:49 -07:00
HexagonTargetTransformInfo.h [TTI][ARM][MVE] Refine gather/scatter cost model 2020-03-11 10:23:41 +00:00
HexagonVectorLoopCarriedReuse.cpp
HexagonVectorPrint.cpp [Hexagon] v67+ HVX register pairs should support either direction 2020-02-14 12:43:43 -06:00
HexagonVExtract.cpp
HexagonVLIWPacketizer.cpp [MC] Widen the functional unit type from 32 to 64 bits. 2020-02-24 09:37:00 +01:00
HexagonVLIWPacketizer.h [Hexagon] Add support for Hexagon v67t microarchitecture (tiny core) 2020-01-21 11:35:10 -06:00
LLVMBuild.txt
RDFCopy.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
RDFCopy.h Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
RDFDeadCode.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
RDFDeadCode.h Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00