Craig Topper 838aaca549 [X86] Teach EltsFromConsecutiveLoads that it's ok to form a v4f32 VZEXT_LOAD with a 64 bit memory size on SSE1 targets. ... We can use MOVLPS which will load 64 bits, but we need a v4f32 result type. We already have isel patterns for this. The code here is a little hacky. We can probably improve it with more isel patterns.		2020-02-22 18:50:52 -08:00
..
AArch64	[AArch64][SVE] Add support for DestructiveBinary and DestructiveBinaryComm DestructiveInstTypes	2020-02-21 15:19:54 -06:00
AMDGPU	Revert "[AMDGPU] Don’t marke the .note section as ALLOC"	2020-02-21 16:08:30 -08:00
ARC
ARM	Regenerate rotate test. NFC.	2020-02-20 13:54:43 +00:00
AVR
BPF
Generic
Hexagon	[Hexagon] Introduce noop intrinsic to cast between vector predicate types	2020-02-21 07:37:59 -06:00
Inputs
Lanai
Mips	[MIPS GlobalISel] Legalize non-power-of-2 and unaligned load and store	2020-02-19 12:02:27 +01:00
MIR	Revert "Reland "[DebugInfo] Enable the debug entry values feature by default""	2020-02-20 14:41:39 +01:00
MSP430
NVPTX
PowerPC	[XCOFF][AIX] Put undefined symbol name into StringTable when neccessary	2020-02-21 18:18:31 +00:00
RISCV	[RISCV] Implement mayBeEmittedAsTailCall for tail call optimization	2020-02-18 23:56:42 +08:00
SPARC
SystemZ	[ValueTracking] Improve isKnownNonNaN() to recognize zero splats.	2020-02-19 09:35:36 -08:00
Thumb	Use SETNE directly rather than SUB/SETNE 0 for stack guard check	2020-02-18 13:21:26 +00:00
Thumb2	[ARM,MVE] Add vqdmull[b,t]q intrinsic families	2020-02-20 10:51:19 +00:00
VE	[VE] TLS codegen	2020-02-18 16:09:12 +01:00
WebAssembly	[WebAssembly] Replace all calls with generalized multivalue calls	2020-02-18 15:55:20 -08:00
WinCFGuard
WinEH
X86	[X86] Teach EltsFromConsecutiveLoads that it's ok to form a v4f32 VZEXT_LOAD with a 64 bit memory size on SSE1 targets.	2020-02-22 18:50:52 -08:00
XCore	[XCore] Add instruction pattern for bitrev	2020-02-21 09:28:49 +08:00