1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
llvm-mirror/test/CodeGen/Hexagon/addrmode-rr-to-io.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

23 lines
485 B
YAML

# RUN: llc -march=hexagon -run-pass amode-opt %s -o - | FileCheck %s
# This testcase used to crash.
# CHECK: S2_storerb_io killed $r0, @var_i8, killed $r2
--- |
define void @fred() { ret void }
@var_i8 = global [10 x i8] zeroinitializer, align 8
...
---
name: fred
tracksRegLiveness: true
body: |
bb.0:
liveins: $r0
$r1 = A2_tfrsi @var_i8
$r2 = A2_tfrsi 255
S4_storerb_rr killed $r0, killed $r1, 0, killed $r2
PS_jmpret $r31, implicit-def $pc
...