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45dd9c1c1d
It should be enabled only when the load alignment is at least 8-byte. Fixes: SWDEV-256824 Reviewed By: foad Differential Revision: https://reviews.llvm.org/D90404
72 lines
2.9 KiB
LLVM
72 lines
2.9 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; The type promotion for the vector loads v3i32/v3f32 into v4i32/v4f32 is enabled
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; only when the alignment is 8-byte or higher.
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; Otherwise, split the load into two separate loads (dwordx2 + dword).
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; This type promotion on smaller aligned loads can cause a page fault error
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; while accessing one extra dword beyond the buffer.
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define protected amdgpu_kernel void @load_v3i32_align4(<3 x i32> addrspace(1)* %arg) #0 {
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; GCN-LABEL: load_v3i32_align4:
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; GCN: ; %bb.0:
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; GCN: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx2 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x0
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; GCN-NEXT: s_load_dword s{{[0-9]+}}, s[0:1], 0x8
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%vec = load <3 x i32>, <3 x i32> addrspace(1)* %arg, align 4
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store <3 x i32> %vec, <3 x i32> addrspace(1)* undef, align 4
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ret void
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}
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define protected amdgpu_kernel void @load_v3i32_align8(<3 x i32> addrspace(1)* %arg) #0 {
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; GCN-LABEL: load_v3i32_align8:
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; GCN: ; %bb.0:
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; GCN: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x0
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%vec = load <3 x i32>, <3 x i32> addrspace(1)* %arg, align 8
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store <3 x i32> %vec, <3 x i32> addrspace(1)* undef, align 8
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ret void
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}
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define protected amdgpu_kernel void @load_v3i32_align16(<3 x i32> addrspace(1)* %arg) #0 {
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; GCN-LABEL: load_v3i32_align16:
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; GCN: ; %bb.0:
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; GCN: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x0
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%vec = load <3 x i32>, <3 x i32> addrspace(1)* %arg, align 16
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store <3 x i32> %vec, <3 x i32> addrspace(1)* undef, align 16
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ret void
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}
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define protected amdgpu_kernel void @load_v3f32_align4(<3 x float> addrspace(1)* %arg) #0 {
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; GCN-LABEL: load_v3f32_align4:
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; GCN: ; %bb.0:
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; GCN: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx2 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x0
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; GCN-NEXT: s_load_dword s{{[0-9]+}}, s[0:1], 0x8
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%vec = load <3 x float>, <3 x float> addrspace(1)* %arg, align 4
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store <3 x float> %vec, <3 x float> addrspace(1)* undef, align 4
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ret void
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}
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define protected amdgpu_kernel void @load_v3f32_align8(<3 x float> addrspace(1)* %arg) #0 {
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; GCN-LABEL: load_v3f32_align8:
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; GCN: ; %bb.0:
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; GCN: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x0
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%vec = load <3 x float>, <3 x float> addrspace(1)* %arg, align 8
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store <3 x float> %vec, <3 x float> addrspace(1)* undef, align 8
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ret void
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}
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define protected amdgpu_kernel void @load_v3f32_align16(<3 x float> addrspace(1)* %arg) #0 {
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; GCN-LABEL: load_v3f32_align16:
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; GCN: ; %bb.0:
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; GCN: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x0
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%vec = load <3 x float>, <3 x float> addrspace(1)* %arg, align 16
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store <3 x float> %vec, <3 x float> addrspace(1)* undef, align 16
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ret void
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}
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attributes #0 = { nounwind noinline }
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