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"To" selects an odd-numbered GPR, and "Te" an even one. There are some 8.1-M instructions that have one too few bits in their register fields and require registers of particular parity, without necessarily using a consecutive even/odd pair. Also, the constraint letter "t" should select an MVE q-register, when MVE is present. This didn't need any source changes, but some extra tests have been added. Reviewers: dmgreen, samparker, SjoerdMeijer Subscribers: javed.absar, eraman, kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D60709 llvm-svn: 364331
49 lines
1.7 KiB
LLVM
49 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=armv8.1-m-eabi -mattr=+mve %s -o - | FileCheck %s
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define i32 @test1(i32 %tmp54) {
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%tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 )
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ret i32 %tmp56
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}
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define void @test2() {
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tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )
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ret void
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}
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define arm_aapcs_vfpcc <4 x i32> @mve-t-constraint-128bit(<4 x i32>, <4 x i32>) {
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; CHECK-LABEL: mve-t-constraint-128bit
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; CHECK: vadd.i32 q{{[0-7]}}, q{{[0-7]}}, q{{[0-7]}}
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%ret = tail call <4 x i32>
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asm "vadd.i32 $0, $1, $2", "=t,t,t"
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(<4 x i32> %0, <4 x i32> %1)
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ret <4 x i32> %ret
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}
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define i32 @even-GPR-constraint() {
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entry:
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; CHECK-LABEL: even-GPR-constraint
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; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #1
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; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #2
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; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #3
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; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #4
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%0 = tail call { i32, i32, i32, i32 }
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asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^Te,=^Te,=^Te,=^Te,0,1,2,3"
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(i32 0, i32 0, i32 0, i32 0)
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%asmresult = extractvalue { i32, i32, i32, i32 } %0, 0
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ret i32 %asmresult
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}
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define i32 @odd-GPR-constraint() {
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entry:
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; CHECK-LABEL: odd-GPR-constraint
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; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #1
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; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #2
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; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #3
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; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #4
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%0 = tail call { i32, i32, i32, i32 }
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asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^To,=^To,=^To,=^To,0,1,2,3"
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(i32 0, i32 0, i32 0, i32 0)
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%asmresult = extractvalue { i32, i32, i32, i32 } %0, 0
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ret i32 %asmresult
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}
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