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llvm-mirror/test/MC/Disassembler
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Lei Huang bbc51b9f17 [PowerPC]Add addex instruction definition and MC tests 
Add td definitions and asm/disasm tests for the addex instruction introduced in
ISA 3.0.

Reviewed By: nemanjai, amyk, NeHuang

Differential Revision: https://reviews.llvm.org/D106666
2021-07-26 14:55:38 -05:00
..
AArch64 [Aarch64] Adding support for Armv9-A Realm Management Extension 2021-06-28 13:45:22 +01:00
AMDGPU [AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions 2021-07-22 10:42:15 +09:00
ARC [ARC] Add tablegen definition for the Find Leading Set (FLS) instruction 2021-07-22 17:42:25 -07:00
ARM [ARMInstPrinter] Print the target address of a branch instruction 2021-06-30 16:35:28 +07:00
Hexagon
Lanai
M68k [M68k] Implement Disassembler 2021-04-19 22:24:12 +01:00
Mips [mips] Add tests to check disassembling of add.ps/mul.ps/sub.ps instructions 2020-11-13 14:31:12 +03:00
MSP430
PowerPC [PowerPC]Add addex instruction definition and MC tests 2021-07-26 14:55:38 -05:00
RISCV [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
Sparc
SystemZ [SystemZ] Add support for new cpu architecture - arch14 2021-07-26 16:57:28 +02:00
WebAssembly [WebAssembly] Update v128.any_true 2021-04-11 11:13:16 -07:00
X86 [X86] Fix disassembly of x86-64 GDTLS code sequence 2021-02-02 11:35:00 +00:00
XCore