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llvm-mirror/test/MC/Disassembler/RISCV
Craig Topper 218109597e [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump
This makes the llvm-objdump output much more readable and closer to binutils objdump. This builds on D76591

It requires changing the OperandType for certain immediates to "OPERAND_PCREL" so tablegen will generate code to pass the instruction's address. This means we can't do the generic check on these instructions in verifyInstruction any more. Should I add it back with explicit opcode checks? Or should we add a new operand flag to control the passing of address instead of matching the name?

Differential Revision: https://reviews.llvm.org/D92147
2020-12-04 10:34:12 -08:00
..
branch-targets.txt
fuzzer-invalid.txt
invalid-fp-rounding-mode.txt
invalid-instruction.txt
lit.local.cfg
unknown-fence-field.txt