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llvm-mirror/test/MC/Disassembler/X86/avx_vnni.txt
Liu, Chen3 0f29f1e458 [X86] Support Intel avxvnni
This patch mainly made the following changes:

1. Support AVX-VNNI instructions;
2. Introduce ExplicitVEXPrefix flag so that vpdpbusd/vpdpbusds/vpdpbusds/vpdpbusds instructions only use vex-encoding when user explicity add {vex} prefix.

Differential Revision: https://reviews.llvm.org/D89105
2020-10-31 12:39:51 +08:00

171 lines
5.3 KiB
Plaintext

# RUN: llvm-mc --disassemble %s -triple=i686-apple-darwin9 | FileCheck %s
# CHECK: {vex} vpdpbusd %ymm4, %ymm5, %ymm6
0xc4,0xe2,0x55,0x50,0xf4
# CHECK: {vex} vpdpbusd %xmm4, %xmm5, %xmm6
0xc4,0xe2,0x51,0x50,0xf4
# CHECK: {vex} vpdpbusd 268435456(%esp,%esi,8), %ymm5, %ymm6
0xc4,0xe2,0x55,0x50,0xb4,0xf4,0x00,0x00,0x00,0x10
# CHECK: {vex} vpdpbusd 291(%edi,%eax,4), %ymm5, %ymm6
0xc4,0xe2,0x55,0x50,0xb4,0x87,0x23,0x01,0x00,0x00
# CHECK: {vex} vpdpbusd (%eax), %ymm5, %ymm6
0xc4,0xe2,0x55,0x50,0x30
# CHECK: {vex} vpdpbusd -1024(,%ebp,2), %ymm5, %ymm6
0xc4,0xe2,0x55,0x50,0x34,0x6d,0x00,0xfc,0xff,0xff
# CHECK: {vex} vpdpbusd 4064(%ecx), %ymm5, %ymm6
0xc4,0xe2,0x55,0x50,0xb1,0xe0,0x0f,0x00,0x00
# CHECK: {vex} vpdpbusd -4096(%edx), %ymm5, %ymm6
0xc4,0xe2,0x55,0x50,0xb2,0x00,0xf0,0xff,0xff
# CHECK: {vex} vpdpbusd 268435456(%esp,%esi,8), %xmm5, %xmm6
0xc4,0xe2,0x51,0x50,0xb4,0xf4,0x00,0x00,0x00,0x10
# CHECK: {vex} vpdpbusd 291(%edi,%eax,4), %xmm5, %xmm6
0xc4,0xe2,0x51,0x50,0xb4,0x87,0x23,0x01,0x00,0x00
# CHECK: {vex} vpdpbusd (%eax), %xmm5, %xmm6
0xc4,0xe2,0x51,0x50,0x30
# CHECK: {vex} vpdpbusd -512(,%ebp,2), %xmm5, %xmm6
0xc4,0xe2,0x51,0x50,0x34,0x6d,0x00,0xfe,0xff,0xff
# CHECK: {vex} vpdpbusd 2032(%ecx), %xmm5, %xmm6
0xc4,0xe2,0x51,0x50,0xb1,0xf0,0x07,0x00,0x00
# CHECK: {vex} vpdpbusd -2048(%edx), %xmm5, %xmm6
0xc4,0xe2,0x51,0x50,0xb2,0x00,0xf8,0xff,0xff
# CHECK: {vex} vpdpbusds %ymm4, %ymm5, %ymm6
0xc4,0xe2,0x55,0x51,0xf4
# CHECK: {vex} vpdpbusds %xmm4, %xmm5, %xmm6
0xc4,0xe2,0x51,0x51,0xf4
# CHECK: {vex} vpdpbusds 268435456(%esp,%esi,8), %ymm5, %ymm6
0xc4,0xe2,0x55,0x51,0xb4,0xf4,0x00,0x00,0x00,0x10
# CHECK: {vex} vpdpbusds 291(%edi,%eax,4), %ymm5, %ymm6
0xc4,0xe2,0x55,0x51,0xb4,0x87,0x23,0x01,0x00,0x00
# CHECK: {vex} vpdpbusds (%eax), %ymm5, %ymm6
0xc4,0xe2,0x55,0x51,0x30
# CHECK: {vex} vpdpbusds -1024(,%ebp,2), %ymm5, %ymm6
0xc4,0xe2,0x55,0x51,0x34,0x6d,0x00,0xfc,0xff,0xff
# CHECK: {vex} vpdpbusds 4064(%ecx), %ymm5, %ymm6
0xc4,0xe2,0x55,0x51,0xb1,0xe0,0x0f,0x00,0x00
# CHECK: {vex} vpdpbusds -4096(%edx), %ymm5, %ymm6
0xc4,0xe2,0x55,0x51,0xb2,0x00,0xf0,0xff,0xff
# CHECK: {vex} vpdpbusds 268435456(%esp,%esi,8), %xmm5, %xmm6
0xc4,0xe2,0x51,0x51,0xb4,0xf4,0x00,0x00,0x00,0x10
# CHECK: {vex} vpdpbusds 291(%edi,%eax,4), %xmm5, %xmm6
0xc4,0xe2,0x51,0x51,0xb4,0x87,0x23,0x01,0x00,0x00
# CHECK: {vex} vpdpbusds (%eax), %xmm5, %xmm6
0xc4,0xe2,0x51,0x51,0x30
# CHECK: {vex} vpdpbusds -512(,%ebp,2), %xmm5, %xmm6
0xc4,0xe2,0x51,0x51,0x34,0x6d,0x00,0xfe,0xff,0xff
# CHECK: {vex} vpdpbusds 2032(%ecx), %xmm5, %xmm6
0xc4,0xe2,0x51,0x51,0xb1,0xf0,0x07,0x00,0x00
# CHECK: {vex} vpdpbusds -2048(%edx), %xmm5, %xmm6
0xc4,0xe2,0x51,0x51,0xb2,0x00,0xf8,0xff,0xff
# CHECK: {vex} vpdpwssd %ymm4, %ymm5, %ymm6
0xc4,0xe2,0x55,0x52,0xf4
# CHECK: {vex} vpdpwssd %xmm4, %xmm5, %xmm6
0xc4,0xe2,0x51,0x52,0xf4
# CHECK: {vex} vpdpwssd 268435456(%esp,%esi,8), %ymm5, %ymm6
0xc4,0xe2,0x55,0x52,0xb4,0xf4,0x00,0x00,0x00,0x10
# CHECK: {vex} vpdpwssd 291(%edi,%eax,4), %ymm5, %ymm6
0xc4,0xe2,0x55,0x52,0xb4,0x87,0x23,0x01,0x00,0x00
# CHECK: {vex} vpdpwssd (%eax), %ymm5, %ymm6
0xc4,0xe2,0x55,0x52,0x30
# CHECK: {vex} vpdpwssd -1024(,%ebp,2), %ymm5, %ymm6
0xc4,0xe2,0x55,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff
# CHECK: {vex} vpdpwssd 4064(%ecx), %ymm5, %ymm6
0xc4,0xe2,0x55,0x52,0xb1,0xe0,0x0f,0x00,0x00
# CHECK: {vex} vpdpwssd -4096(%edx), %ymm5, %ymm6
0xc4,0xe2,0x55,0x52,0xb2,0x00,0xf0,0xff,0xff
# CHECK: {vex} vpdpwssd 268435456(%esp,%esi,8), %xmm5, %xmm6
0xc4,0xe2,0x51,0x52,0xb4,0xf4,0x00,0x00,0x00,0x10
# CHECK: {vex} vpdpwssd 291(%edi,%eax,4), %xmm5, %xmm6
0xc4,0xe2,0x51,0x52,0xb4,0x87,0x23,0x01,0x00,0x00
# CHECK: {vex} vpdpwssd (%eax), %xmm5, %xmm6
0xc4,0xe2,0x51,0x52,0x30
# CHECK: {vex} vpdpwssd -512(,%ebp,2), %xmm5, %xmm6
0xc4,0xe2,0x51,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff
# CHECK: {vex} vpdpwssd 2032(%ecx), %xmm5, %xmm6
0xc4,0xe2,0x51,0x52,0xb1,0xf0,0x07,0x00,0x00
# CHECK: {vex} vpdpwssd -2048(%edx), %xmm5, %xmm6
0xc4,0xe2,0x51,0x52,0xb2,0x00,0xf8,0xff,0xff
# CHECK: {vex} vpdpwssds %ymm4, %ymm5, %ymm6
0xc4,0xe2,0x55,0x53,0xf4
# CHECK: {vex} vpdpwssds %xmm4, %xmm5, %xmm6
0xc4,0xe2,0x51,0x53,0xf4
# CHECK: {vex} vpdpwssds 268435456(%esp,%esi,8), %ymm5, %ymm6
0xc4,0xe2,0x55,0x53,0xb4,0xf4,0x00,0x00,0x00,0x10
# CHECK: {vex} vpdpwssds 291(%edi,%eax,4), %ymm5, %ymm6
0xc4,0xe2,0x55,0x53,0xb4,0x87,0x23,0x01,0x00,0x00
# CHECK: {vex} vpdpwssds (%eax), %ymm5, %ymm6
0xc4,0xe2,0x55,0x53,0x30
# CHECK: {vex} vpdpwssds -1024(,%ebp,2), %ymm5, %ymm6
0xc4,0xe2,0x55,0x53,0x34,0x6d,0x00,0xfc,0xff,0xff
# CHECK: {vex} vpdpwssds 4064(%ecx), %ymm5, %ymm6
0xc4,0xe2,0x55,0x53,0xb1,0xe0,0x0f,0x00,0x00
# CHECK: {vex} vpdpwssds -4096(%edx), %ymm5, %ymm6
0xc4,0xe2,0x55,0x53,0xb2,0x00,0xf0,0xff,0xff
# CHECK: {vex} vpdpwssds 268435456(%esp,%esi,8), %xmm5, %xmm6
0xc4,0xe2,0x51,0x53,0xb4,0xf4,0x00,0x00,0x00,0x10
# CHECK: {vex} vpdpwssds 291(%edi,%eax,4), %xmm5, %xmm6
0xc4,0xe2,0x51,0x53,0xb4,0x87,0x23,0x01,0x00,0x00
# CHECK: {vex} vpdpwssds (%eax), %xmm5, %xmm6
0xc4,0xe2,0x51,0x53,0x30
# CHECK: {vex} vpdpwssds -512(,%ebp,2), %xmm5, %xmm6
0xc4,0xe2,0x51,0x53,0x34,0x6d,0x00,0xfe,0xff,0xff
# CHECK: {vex} vpdpwssds 2032(%ecx), %xmm5, %xmm6
0xc4,0xe2,0x51,0x53,0xb1,0xf0,0x07,0x00,0x00
# CHECK: {vex} vpdpwssds -2048(%edx), %xmm5, %xmm6
0xc4,0xe2,0x51,0x53,0xb2,0x00,0xf8,0xff,0xff