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llvm-mirror/test/TableGen
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Simon Cook bae1c75f0d [TableGen] Support combining AssemblerPredicates with ORs 
For context, the proposed RISC-V bit manipulation extension has a subset
of instructions which require one of two SubtargetFeatures to be
enabled, 'zbb' or 'zbp', and there is no defined feature which both of
these can imply to use as a constraint either (see comments in D65649).

AssemblerPredicates allow multiple SubtargetFeatures to be declared in
the "AssemblerCondString" field, separated by commas, and this means
that the two features must both be enabled. There is no equivalent to
say that _either_ feature X or feature Y must be enabled, short of
creating a dummy SubtargetFeature for this purpose and having features X
and Y imply the new feature.

To solve the case where X or Y is needed without adding a new feature,
and to better match a typical TableGen style, this replaces the existing
"AssemblerCondString" with a dag "AssemblerCondDag" which represents the
same information. Two operators are defined for use with
AssemblerCondDag, "all_of", which matches the current behaviour, and
"any_of", which adds the new proposed ORing features functionality.

This was originally proposed in the RFC at
http://lists.llvm.org/pipermail/llvm-dev/2020-February/139138.html

Changes to all current backends are mechanical to support the replaced
functionality, and are NFCI.

At this stage, it is illegal to combine features with ands and ors in a
single AssemblerCondDag. I suspect this case is sufficiently rare that
adding more complex changes to support it are unnecessary.

Differential Revision: https://reviews.llvm.org/D74338
2020-03-13 17:13:51 +00:00
..
Common [TBLGEN] Emit register pressure set enum 2020-02-18 10:09:05 -08:00
FixedLenDecoderEmitter [TableGen] Correct the shift to the proper bit width. 2019-08-10 16:15:06 +00:00
GICombinerEmitter [gicombiner] Correct 64f1bb5cd2c to account for MSVC's %p format 2020-01-07 12:50:05 -08:00
2003-08-03-PassCode.td
2006-09-18-LargeInt.td
2010-03-24-PrematureDefaults.td
address-space-patfrags.td [GlobalISel] Check LLT size matches memory size for non-truncating stores. 2019-08-02 23:33:13 +00:00
AllowDuplicateRegisterNames.td
ambiguous-composition.td
AnonDefinitionOnDemand.td
arithmetic.td
AsmPredicateCombining.td [TableGen] Support combining AssemblerPredicates with ORs 2020-03-13 17:13:51 +00:00
AsmPredicateCombiningRISCV.td [TableGen] Support combining AssemblerPredicates with ORs 2020-03-13 17:13:51 +00:00
AsmPredicateCondsEmission.td [TableGen] Support combining AssemblerPredicates with ORs 2020-03-13 17:13:51 +00:00
AsmVariant.td
BigEncoder.td Fix compile-time regression caused by rL371928 2019-09-18 18:14:42 +00:00
BitOffsetDecoder.td
BitsInit.td [TableGen] Fix spurious type error in bit assignment. 2020-02-07 15:11:42 +00:00
BitsInitOverflow.td
cast-list-initializer.td
cast-multiclass.td
cast-typeerror.td
cast.td
ClassInstanceValue.td
code.td
compare.td
ConcatenatedSubregs.td
cond-bitlist.td
cond-default.td
cond-empty-list-arg.td
cond-inheritance.td
cond-let.td
cond-list.td
cond-subclass.td
cond-type.td
cond-usage.td
condsbit.td
ConstraintChecking1.td
ConstraintChecking2.td
ConstraintChecking3.td
ConstraintChecking4.td
ConstraintChecking5.td
ConstraintChecking6.td
ConstraintChecking7.td
ConstraintChecking.inc
CStyleComment.td
dag-functional.td
dag-isel-res-order.td
dag-isel-subregs.td [TBLGEN] Fix subreg value overflow in DAGISelMatcher 2020-02-12 13:29:57 -08:00
Dag.td
DAGDefaultOps.td
DefaultOpsGlobalISel.td TableGen: Fix logic for default operands 2020-02-19 23:41:07 -05:00
defmclass.td
DefmInherit.td
DefmInsideMultiClass.td
defset-typeerror.td
defset.td
defvar.td [TableGen] Introduce an if/then/else statement. 2020-01-14 10:19:53 +00:00
duplicate-include.inc Tablegen: Remove the error for duplicate include files. 2019-11-20 18:24:10 -08:00
duplicate-include.td Tablegen: Remove the error for duplicate include files. 2019-11-20 18:24:10 -08:00
DuplicateFieldValues.td
eq-unset.td Fix assertion on !eq(?, 0) 2020-02-18 14:05:55 -08:00
eq.td
eqbit.td
FastISelEmitter.td
field-access-initializers.td [llvm][TableGen] Define FieldInit::isConcrete overload 2020-02-10 18:04:58 -08:00
FieldAccess.td
foldl.td
foreach-eval.td
foreach-leak.td
foreach-multiclass.td
foreach-range-parse-errors0.td
foreach-range-parse-errors1.td
foreach-range-parse-errors2.td
foreach-range-parse-errors3.td
foreach-range-parse-errors4.td
foreach-range-parse-errors5.td
foreach-variable-range.td
foreach.td
ForeachList.td
ForeachLoop.td
ForwardRef.td
GeneralList.td
generic-tables-instruction.td Update tablegen test after r369847. 2019-08-24 15:11:41 +00:00
generic-tables.td [TableGen] Diagnose undefined fields when generating searchable tables 2020-02-19 14:03:48 +00:00
get-operand-type.td [TableGen] Emit OperandType enums for RegisterOperands/RegisterClasses 2019-09-23 18:51:00 +00:00
getsetop.td [TableGen] Add bang-operators !getop and !setop. 2019-12-11 12:05:22 +00:00
gisel-physreg-input.td GlobalISel: Support physical register inputs in patterns 2019-09-06 20:32:37 +00:00
GlobalISelEmitter-immarg-literal-pattern.td TableGen/GlobalISel: Fix pattern matching of immarg literals 2020-01-09 17:37:52 -05:00
GlobalISelEmitter-input-discard.td TableGen/GlobalISel: Don't check exact intrinsic opcode value 2020-01-17 20:09:53 -05:00
GlobalISelEmitter-PR39045.td [GlobalISel][NFC] Factor out common target code from GlobalISelEmitterTests 2019-08-13 22:14:37 +00:00
GlobalISelEmitter-SDNodeXForm-timm.td TableGen/GlobalISel: Add way for SDNodeXForm to work on timm 2020-01-09 17:37:52 -05:00
GlobalISelEmitter-setcc.td GlobalISel/TableGen: Handle setcc patterns 2019-08-29 01:13:41 +00:00
GlobalISelEmitter.td TableGen/GlobalISel: Add way for SDNodeXForm to work on timm 2020-01-09 17:37:52 -05:00
GlobalISelEmitterOverloadedPtr.td Teach GlobalISelEmitter to treat used iPTRAny operands as pointer operands 2019-08-20 22:04:10 +00:00
GlobalISelEmitterRegSequence.td GlobalISel/TableGen: Handle REG_SEQUENCE patterns 2019-09-10 17:57:33 +00:00
GlobalISelEmitterSkippedPatterns.td [GlobalISel][NFC] Factor out common target code from GlobalISelEmitterTests 2019-08-13 22:14:37 +00:00
GlobalISelEmitterSubreg.td TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG 2020-01-24 12:15:10 -08:00
GlobalISelEmitterVariadic.td [GlobalISel] Match table opt: fix a bug in matching num of operands 2019-11-01 01:57:48 -07:00
HwModeEncodeDecode.td [TableGen] Fix crash when using HwModes in CodeEmitterGen 2019-10-09 09:15:34 +00:00
HwModeSelect.td Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
if-empty-list-arg.td
if-type.td
if.td
ifbit.td
ifstmt.td [TableGen] Introduce an if/then/else statement. 2020-01-14 10:19:53 +00:00
immarg.td Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics" 2019-09-19 16:26:14 +00:00
Include.inc
Include.td
inhibit-pset.td [TBLGEN] Inhibit generation of unneeded psets 2020-02-17 15:38:08 -08:00
IntBitInit.td
intrin-side-effects.td [TableGen] Do not set ReadNone attribute on intrinsics with side effects 2019-07-17 10:53:13 +00:00
intrinsic-long-name.td [IR] Split out target specific intrinsic enums into separate headers 2019-12-11 18:02:14 -08:00
intrinsic-pointer-to-any.td
intrinsic-struct.td [IR] Split out target specific intrinsic enums into separate headers 2019-12-11 18:02:14 -08:00
intrinsic-varargs.td [TableGen] Include ValueTypes.td directly into the intrinsic-varargs.td test. 2019-08-21 19:14:38 +00:00
IntSpecialValues.td
InvalidMCSchedClassDesc.td [TableGen] Fix a bug that MCSchedClassDesc is interfered between different SchedModel 2019-10-11 08:36:54 +00:00
isa.td
JSON-check.py
JSON.td
LazyChange.td
LetInsideMultiClasses.td
lisp.td
list-element-bitref.td
ListArgs.td
ListArgsSimple.td
listconcat.td
ListConversion.td
ListManip.td
ListOfList.td
listpaste.td
ListSlices.td
listsplat.td
lit.local.cfg Attempt to fix issue with unresolved lit test in TableGen 2019-08-13 22:32:26 +00:00
LoLoL.td
math.td
MultiClass-def-fail.td
MultiClass-defm-fail.td
MultiClass-defm.td
MultiClass.td
MultiClassDefName.td
MultiClassInherit.td
MultiPat.td
name-resolution-consistency.td
nested-comment.td
NestedForeach.td
Paste.td
pr8330.td
predicate-patfags.td TableGen: Fix assert on PatFrags with predicate code 2019-12-30 14:24:25 -05:00
prep-diag1.td
prep-diag2.td
prep-diag3.td
prep-diag4.td
prep-diag5.td
prep-diag6.td
prep-diag7.td
prep-diag8.td
prep-diag9.td
prep-diag10.td
prep-diag11-include.inc
prep-diag11.td
prep-diag12-include.inc
prep-diag12.td
prep-diag13.td
prep-diag14.td
prep-ifndef-diag-1.td
prep-ifndef-diag-2.td
prep-ifndef.td
prep-region-include.inc
prep-region-processing.td
pset-enum.td [TBLGEN] Emit register pressure set enum 2020-02-18 10:09:05 -08:00
rc-weight-override.td [TBLGEN] Allow to override RC weight 2020-02-14 15:49:52 -08:00
RegisterBankEmitter.td
RegisterEncoder.td [CodeEmitter] Support instruction widths > 64 bits 2019-09-15 08:35:08 +00:00
RelTest.td
SchedModelError.td
searchabletables-intrinsic.td
self-reference-recursion.td
self-reference-typeerror.td
self-reference.td
SetTheory.td
SiblingForeach.td
simplify-patfrag.td [TableGen] Don't elide bitconverts in PatFrag fragments. 2020-02-17 09:30:45 +00:00
size.td
Slice.td
strconcat.td
String.td
subst2.td
subst.td
SuperSubclassSameName.td
TargetInstrInfo.td
TargetInstrSpec.td
template-arg-dependency.td
TemplateArgRename.td
Tree.td
TreeNames.td
trydecode-emission2.td
trydecode-emission3.td
trydecode-emission.td
TwoLevelName.td
UnsetBitInit.td
unsetop.td [TableGen] Permit dag operators to be unset. 2019-12-10 11:09:40 +00:00
unterminated-c-comment-include.inc
unterminated-c-comment.td
unterminated-code-block-include.inc
unterminated-code-block.td
UnterminatedComment.td
usevalname.td
ValidIdentifiers.td