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96a200f6e7
llvm-mirror/lib/Target/AMDGPU
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Matt Arsenault 96a200f6e7 AMDGPU: Implement SGPR spilling with scalar stores 
nThis avoids the nasty problems caused by using
memory instructions that read the exec mask while
spilling / restoring registers used for control flow
masking, but only for VI when these were added.

This always uses the scalar stores when enabled currently,
but it may be better to still try to spill to a VGPR
and use this on the fallback memory path.

The cache also needs to be flushed before wave termination
if a scalar store is used.

llvm-svn: 286766
2016-11-13 18:20:54 +00:00
..
AsmParser [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
Disassembler AMDGPU: Whitespace fixes 2016-11-01 00:55:14 +00:00
InstPrinter [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions. 2016-10-31 16:07:39 +00:00
MCTargetDesc [AMDGPU] TargetStreamer: Fix .note section name 2016-11-11 13:41:52 +00:00
TargetInfo Move the global variables representing each Target behind accessor function 2016-10-09 23:00:34 +00:00
Utils AMDGPU/SI: Handle hazard with > 8 byte VMEM stores 2016-10-27 23:05:31 +00:00
AMDGPU.h Move the global variables representing each Target behind accessor function 2016-10-09 23:00:34 +00:00
AMDGPU.td [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
AMDGPUAlwaysInlinePass.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
AMDGPUAnnotateKernelFeatures.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
AMDGPUAnnotateUniformValues.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
AMDGPUAsmPrinter.cpp AMDGPU: Emit runtime metadata as a note element in .note section 2016-11-10 21:18:49 +00:00
AMDGPUAsmPrinter.h AMDGPU: Emit runtime metadata as a note element in .note section 2016-11-10 21:18:49 +00:00
AMDGPUCallingConv.td
AMDGPUCallLowering.cpp GlobalISel: pass Function to lowerFormalArguments directly (NFC). 2016-09-21 12:57:35 +00:00
AMDGPUCallLowering.h GlobalISel: pass Function to lowerFormalArguments directly (NFC). 2016-09-21 12:57:35 +00:00
AMDGPUCodeGenPrepare.cpp [AMDGPU] AMDGPUCodeGenPrepare: remove extra ';' 2016-10-07 14:39:53 +00:00
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp [AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx to AMDGPUBaseInfo.h 2016-10-07 14:46:06 +00:00
AMDGPUInstrInfo.h [AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx to AMDGPUBaseInfo.h 2016-10-07 14:46:06 +00:00
AMDGPUInstrInfo.td AMDGPU: Select mulhi 24-bit instructions 2016-08-27 01:32:27 +00:00
AMDGPUInstructions.td [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp AMDGPU: Remove unnecessary and on conditional branch 2016-11-07 19:09:33 +00:00
AMDGPUISelLowering.cpp [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
AMDGPUISelLowering.h [DAG Combiner] Fix the native computation of the Newton series for reciprocals 2016-11-10 23:31:06 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp [AMDGPU] Emit 32-bit lo/hi got and pc relative variant kinds for external and global address space variables 2016-10-14 04:37:34 +00:00
AMDGPUMCInstLower.h Reapply "AMDGPU: Support using tablegened MC pseudo expansions" 2016-10-06 17:19:11 +00:00
AMDGPUOpenCLImageTypeLoweringPass.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
AMDGPUPromoteAlloca.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
AMDGPUPTNote.h AMDGPU: Emit runtime metadata as a note element in .note section 2016-11-10 21:18:49 +00:00
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPURuntimeMetadata.h AMDGPU: Attempt to fix build failure on x86-64 selfhost build 2016-11-11 02:48:50 +00:00
AMDGPUSubtarget.cpp [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
AMDGPUSubtarget.h [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
AMDGPUTargetMachine.cpp Move the global variables representing each Target behind accessor function 2016-10-09 23:00:34 +00:00
AMDGPUTargetMachine.h
AMDGPUTargetObjectFile.cpp Target: Change various section classifiers in TargetLoweringObjectFile to take a GlobalObject. 2016-10-24 19:23:39 +00:00
AMDGPUTargetObjectFile.h Target: Change various section classifiers in TargetLoweringObjectFile to take a GlobalObject. 2016-10-24 19:23:39 +00:00
AMDGPUTargetTransformInfo.cpp Add new target hooks for LoadStoreVectorizer 2016-10-03 10:31:34 +00:00
AMDGPUTargetTransformInfo.h Do a sweep over move ctors and remove those that are identical to the default. 2016-10-20 12:20:28 +00:00
AMDILCFGStructurizer.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
AMDKernelCodeT.h
BUFInstructions.td AMDGPU: Add VI i16 support 2016-11-10 16:02:37 +00:00
CaymanInstructions.td AMDGPU: Select mulhi 24-bit instructions 2016-08-27 01:32:27 +00:00
CIInstructions.td [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions 2016-09-23 09:08:07 +00:00
CMakeLists.txt Reapply "AMDGPU: Support using tablegened MC pseudo expansions" 2016-10-06 17:19:11 +00:00
DSInstructions.td AMDGPU: Add VI i16 support 2016-11-10 16:02:37 +00:00
EvergreenInstructions.td AMDGPU: Select mulhi 24-bit instructions 2016-08-27 01:32:27 +00:00
FLATInstructions.td AMDGPU: Add VI i16 support 2016-11-10 16:02:37 +00:00
GCNHazardRecognizer.cpp AMDGPU/SI: Handle hazard with s_rfe_b64 2016-10-27 23:50:21 +00:00
GCNHazardRecognizer.h AMDGPU/SI: Handle hazard with s_rfe_b64 2016-10-27 23:50:21 +00:00
GCNSchedStrategy.cpp AMDGPU: Whitespace fixes 2016-11-01 00:55:14 +00:00
GCNSchedStrategy.h AMDGPU/SI: Implement a custom MachineSchedStrategy 2016-08-29 19:42:52 +00:00
LLVMBuild.txt
MIMGInstructions.td AMDGPU: Rename glc operand type 2016-10-28 21:55:08 +00:00
Processors.td AMDGPU: Refactor processor definition to use ISA version features 2016-10-26 16:37:56 +00:00
R600ClauseMergePass.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
R600ControlFlowFinalizer.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
R600Defines.h
R600EmitClauseMarkers.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
R600ExpandSpecialInstrs.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
R600FrameLowering.cpp
R600FrameLowering.h
R600InstrFormats.td
R600InstrInfo.cpp Finish renaming remaining analyzeBranch functions 2016-09-14 20:43:16 +00:00
R600InstrInfo.h Finish renaming remaining analyzeBranch functions 2016-09-14 20:43:16 +00:00
R600Instructions.td Target: Remove unused patterns and transforms. NFC. 2016-10-07 00:30:49 +00:00
R600Intrinsics.td
R600ISelLowering.cpp AMDGPU: Refactor kernel argument lowering 2016-09-16 21:53:00 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
R600Packetizer.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R700Instructions.td
SIAnnotateControlFlow.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SIDebuggerInsertNops.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SIDefines.h AMDGPU: Workaround for instruction size with literals 2016-11-01 20:42:24 +00:00
SIFixControlFlowLiveIntervals.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SIFixSGPRCopies.cpp AMDGPU/SI: Fix visit order assumption in SIFixSGPRCopies 2016-11-11 23:35:42 +00:00
SIFoldOperands.cpp [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
SIFrameLowering.cpp AMDGPU: Fix using incorrect private resource with no allocation 2016-10-28 19:43:31 +00:00
SIFrameLowering.h AMDGPU: Refactor frame lowering 2016-08-31 21:52:21 +00:00
SIInsertSkips.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SIInsertWaits.cpp AMDGPU: Implement SGPR spilling with scalar stores 2016-11-13 18:20:54 +00:00
SIInstrFormats.td AMDGPU: Workaround for instruction size with literals 2016-11-01 20:42:24 +00:00
SIInstrInfo.cpp AMDGPU: Implement SGPR spilling with scalar stores 2016-11-13 18:20:54 +00:00
SIInstrInfo.h AMDGPU: Workaround for instruction size with literals 2016-11-01 20:42:24 +00:00
SIInstrInfo.td [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
SIInstructions.td [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
SIIntrinsics.td AMDGPU: Allow some control flow intrinsics to be CSEd 2016-09-16 22:11:18 +00:00
SIISelLowering.cpp [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
SIISelLowering.h [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
SILoadStoreOptimizer.cpp [AMDGPU][CodeGen] To improve CGEMM performance: combine LDS reads. 2016-11-03 14:37:13 +00:00
SILowerControlFlow.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SILowerI1Copies.cpp Revert "[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate condition copies" 2016-11-11 00:22:34 +00:00
SIMachineFunctionInfo.cpp AMDGPU/SI: Add support for triples with the mesa3d operating system 2016-09-16 21:34:26 +00:00
SIMachineFunctionInfo.h [AMDGPU] Wave and register controls 2016-09-06 20:22:28 +00:00
SIMachineScheduler.cpp
SIMachineScheduler.h
SIOptimizeExecMasking.cpp AMDGPU: Fix use-after-free in SIOptimizeExecMasking 2016-10-07 08:40:14 +00:00
SIRegisterInfo.cpp AMDGPU: Implement SGPR spilling with scalar stores 2016-11-13 18:20:54 +00:00
SIRegisterInfo.h AMDGPU: Refactor copyPhysReg 2016-11-07 16:39:22 +00:00
SIRegisterInfo.td [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
SISchedule.td AMDGPU/SI: Implement a custom MachineSchedStrategy 2016-08-29 19:42:52 +00:00
SIShrinkInstructions.cpp [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
SITypeRewriter.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SIWholeQuadMode.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
SMInstructions.td [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions. 2016-10-31 16:07:39 +00:00
SOPInstructions.td AMDGPU: Add VI i16 support 2016-11-10 16:02:37 +00:00
VIInstrFormats.td [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions 2016-09-23 09:08:07 +00:00
VIInstructions.td AMDGPU: Add VI i16 support 2016-11-10 16:02:37 +00:00
VOP1Instructions.td [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
VOP2Instructions.td [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
VOP3Instructions.td [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
VOPCInstructions.td [AMDGPU] Add f16 support (VI+) 2016-11-13 07:01:11 +00:00
VOPInstructions.td [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions 2016-09-23 09:08:07 +00:00