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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
40 lines
1.5 KiB
YAML
40 lines
1.5 KiB
YAML
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
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--- |
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@var_i32 = global i32 42
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@var_i64 = global i64 0
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define void @sub_small() {
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entry:
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%val32 = load i32, i32* @var_i32
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%newval32 = sub i32 %val32, 4095
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store i32 %newval32, i32* @var_i32
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%val64 = load i64, i64* @var_i64
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%newval64 = sub i64 %val64, 52
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store i64 %newval64, i64* @var_i64
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ret void
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}
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...
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---
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name: sub_small
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body: |
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bb.0.entry:
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; CHECK: $x8 = ADRP target-flags(aarch64-page) @var_i32
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; CHECK-NEXT: $x9 = ADRP target-flags(aarch64-page) @var_i64
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; CHECK-NEXT: $w10 = LDRWui $x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
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; CHECK-NEXT: $x11 = LDRXui $x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64
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; CHECK: STRWui killed $w10, killed $x8, target-flags(aarch64-nc) @var_i32
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; CHECK: STRXui killed $x11, killed $x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64
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$x8 = ADRP target-flags(aarch64-page) @var_i32
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$x9 = ADRP target-flags(aarch64-page) @var_i64
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$w10 = LDRWui $x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32
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$x11 = LDRXui $x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64
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$w10 = SUBWri killed $w10, 4095, 0
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$x11 = SUBXri killed $x11, 52, 0
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STRWui killed $w10, killed $x8, target-flags(aarch64-nc) @var_i32
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STRXui killed $x11, killed $x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64
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RET_ReallyLR
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...
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