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llvm-mirror/test/CodeGen/Thumb2
Sam Tebbs e397da3290 [ARM][LowOverheadLoops] Convert intermediate vpr use assertion to condition
This converts the intermediate VPR use assertion to a condition in the if-statement to protect against assertion failures in case behaviuour is changed.

This is a follow-up to https://reviews.llvm.org/D90935 and implements the post-approval comments.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D91790
2020-11-19 17:15:45 +00:00
..
LowOverheadLoops [ARM][LowOverheadLoops] Convert intermediate vpr use assertion to condition 2020-11-19 17:15:45 +00:00
mve-intrinsics [InstCombine] Move target-specific inst combining 2020-07-22 15:59:49 +02:00
2009-07-17-CrossRegClassCopy.ll
2009-07-21-ISelBug.ll
2009-07-23-CPIslandBug.ll
2009-07-30-PEICrash.ll
2009-08-01-WrongLDRBOpc.ll
2009-08-02-CoalescerBug.ll
2009-08-04-CoalescerAssert.ll
2009-08-04-CoalescerBug.ll
2009-08-04-ScavengerAssert.ll
2009-08-04-SubregLoweringBug2.ll
2009-08-04-SubregLoweringBug3.ll
2009-08-04-SubregLoweringBug.ll
2009-08-06-SpDecBug.ll
2009-08-07-CoalescerBug.ll
2009-08-07-NeonFPBug.ll
2009-08-08-ScavengerAssert.ll
2009-08-10-ISelBug.ll
2009-08-21-PostRAKill4.ll
2009-09-01-PostRAProlog.ll
2009-10-15-ITBlockBranch.ll
2009-11-01-CopyReg2RegBug.ll
2009-11-11-ScavengerAssert.ll
2009-11-13-STRDBug.ll
2009-12-01-LoopIVUsers.ll
2010-01-06-TailDuplicateLabels.ll
2010-01-19-RemovePredicates.ll
2010-02-11-phi-cycle.ll
2010-02-24-BigStack.ll
2010-03-08-addi12-ccout.ll
2010-03-15-AsmCCClobber.ll
2010-04-15-DynAllocBug.ll
2010-04-26-CopyRegCrash.ll
2010-05-24-rsbs.ll
2010-06-14-NEONCoalescer.ll
2010-06-19-ITBlockCrash.ll
2010-06-21-TailMergeBug.ll
2010-08-10-VarSizedAllocaBug.ll
2010-11-22-EpilogueBug.ll
2010-12-03-AddSPNarrowing.ll
2011-04-21-FILoweringBug.ll
2011-06-07-TwoAddrEarlyClobber.ll
2011-12-16-T2SizeReduceAssert.ll
2012-01-13-CBNZBug.ll
2013-02-19-tail-call-register-hint.ll
2013-03-02-vduplane-nonconstant-source-index.ll
2013-03-06-vector-sext-operand-scalarize.ll
aapcs.ll
active_lane_mask.ll [ARM] Fixup of a few test cases. NFC. 2020-09-09 11:14:44 +01:00
aligned-constants.ll
aligned-spill.ll
bfi.ll
bfx.ll
bicbfi.ll
bug-subw.ll
buildvector-crash.ll
call-site-info-update.ll
carry.ll
cbnz.ll
cde-gpr.ll
cde-vec.ll
cde-vfp.ll
cmp-frame.ll
constant-hoisting.ll [ARM] Fix IT block generation after Thumb2SizeReduce with -Oz 2020-10-29 15:17:31 +00:00
constant-islands-cbz.ll
constant-islands-cbz.mir
constant-islands-jump-table.ll
constant-islands-new-island-padding.ll
constant-islands-new-island.ll
constant-islands.ll
cortex-fp.ll
crash.ll
cross-rc-coalescing-1.ll
cross-rc-coalescing-2.ll
csel.ll [ARM] CSEL generation 2020-07-16 11:10:53 +01:00
div.ll
emit-unwinding.ll
fir.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
float-cmp.ll
float-intrinsics-double.ll [ARM] Make tests less dependent on scheduling. NFC 2020-11-05 08:26:55 +00:00
float-intrinsics-float.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
float-ops.ll [ARM] CSEL generation 2020-07-16 11:10:53 +01:00
fp16-stacksplot.mir
frame-index-addrmode-t2i8s4.mir
frame-pointer.ll
frameless2.ll
frameless.ll
high-reg-spill.mir Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
ifcvt-cbz.mir
ifcvt-compare.ll
ifcvt-dead-predicate.mir [ARM] Fix IT block generation after Thumb2SizeReduce with -Oz 2020-10-29 15:17:31 +00:00
ifcvt-minsize.ll
ifcvt-neon-deprecated.mir
ifcvt-no-branch-predictor.ll [ARM] Make tests less dependent on scheduling. NFC 2020-11-05 08:26:55 +00:00
ifcvt-rescan-bug-2016-08-22.ll
ifcvt-rescan-diamonds.ll ARM: make Thumb1 instructions non-flag-setting in IT block. 2020-07-28 13:31:17 +01:00
inflate-regs.ll
inline-asm-i-constraint-i1.ll
inlineasm-error-t-toofewregs-mve.ll
inlineasm-mve.ll
inlineasm.ll
intrinsics-cc.ll
intrinsics-coprocessor.ll
large-call.ll
large-stack.ll
ldr-str-imm12.ll
lit.local.cfg
longMACt.ll
lsll0.ll
lsr-deficiency.ll
m4-sched-ldr.mir
m4-sched-regs.ll
machine-licm.ll
mul_const.ll
mve-abs.ll [SelectionDAG][X86][ARM] Teach ExpandIntRes_ABS to use sra+add+xor expansion when ADDCARRY is supported. 2020-09-07 13:15:26 -07:00
mve-basic.ll
mve-be.ll
mve-bitarith.ll
mve-bitcasts.ll
mve-bitreverse.ll
mve-bswap.ll
mve-ctlz.ll
mve-ctpop.ll
mve-cttz.ll
mve-div-expand.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-extractelt.ll
mve-float16regloops.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-float32regloops.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-fma-loops.ll [ARM] Introduce t2DoLoopStartTP 2020-11-10 18:08:12 +00:00
mve-fmas.ll [ARM] Predicated VFMA patterns 2020-08-12 18:35:01 +01:00
mve-fmath.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-fp16convertloops.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-fp-negabs.ll [SelectionDAG][GISel] Make LegalizeDAG lower FNEG using integer ops. 2020-09-23 14:10:33 -07:00
mve-frint.ll
mve-gather-increment.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
mve-gather-ind8-unscaled.ll [ARM][MVE] Enable MVE gathers and scatters by default 2020-08-28 19:05:29 +01:00
mve-gather-ind16-scaled.ll [ARM][MVE] Enable MVE gathers and scatters by default 2020-08-28 19:05:29 +01:00
mve-gather-ind16-unscaled.ll [ARM][MVE] Enable MVE gathers and scatters by default 2020-08-28 19:05:29 +01:00
mve-gather-ind32-scaled.ll [ARM][MVE] Enable MVE gathers and scatters by default 2020-08-28 19:05:29 +01:00
mve-gather-ind32-unscaled.ll [ARM][MVE] Enable MVE gathers and scatters by default 2020-08-28 19:05:29 +01:00
mve-gather-optimisation-deep.ll [ARM][MVE] Enable MVE gathers and scatters by default 2020-08-28 19:05:29 +01:00
mve-gather-ptrs.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-gather-scatter-opt.ll [ARM][MVE] Enable MVE gathers and scatters by default 2020-08-28 19:05:29 +01:00
mve-gather-scatter-optimisation.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-gather-scatter-ptr-address.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-gather-scatter-tailpred.ll [ARM] Introduce t2DoLoopStartTP 2020-11-10 18:08:12 +00:00
mve-gather-tailpred.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
mve-halving.ll
mve-ldst-offset.ll
mve-ldst-postinc.ll
mve-ldst-preinc.ll
mve-ldst-regimm.ll
mve-loadstore.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-masked-ldst-offset.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-masked-ldst-postinc.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-masked-ldst-preinc.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-masked-ldst.ll [ARM] VCVTT instruction selection 2020-06-26 08:58:55 +01:00
mve-masked-load.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-masked-store.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-minmax.ll
mve-multivec-spill.ll
mve-neg.ll
mve-nofloat.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-nounrolledremainder.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-phireg.ll [MachineInstr] Add support for instructions with multiple memory operands. 2020-11-03 20:44:40 -05:00
mve-postinc-dct.ll [ARM] Introduce t2DoLoopStartTP 2020-11-10 18:08:12 +00:00
mve-postinc-distribute.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-postinc-distribute.mir [ARM] Expand distributing increments to also handle existing pre/post inc instructions. 2020-09-17 16:58:35 +01:00
mve-postinc-lsr.ll [ARM] Introduce t2DoLoopStartTP 2020-11-10 18:08:12 +00:00
mve-pred-and.ll
mve-pred-bitcast.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-pred-build-const.ll
mve-pred-build-var.ll
mve-pred-const.ll
mve-pred-convert.ll
mve-pred-ext.ll
mve-pred-loadstore.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-pred-not.ll
mve-pred-or.ll
mve-pred-selectop2.ll [ARM] Update target triple in tests. NFC 2020-10-30 15:06:49 +00:00
mve-pred-selectop3.ll [ARM] Update target triple in tests. NFC 2020-10-30 15:06:49 +00:00
mve-pred-selectop.ll [ARM] Update target triple in tests. NFC 2020-10-30 15:06:49 +00:00
mve-pred-shuffle.ll
mve-pred-spill.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-pred-threshold.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-pred-vctpvpsel.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-pred-xor.ll
mve-qrintr.ll [ARM] Sink splats to MVE intrinsics 2020-09-17 16:00:51 +01:00
mve-satmul-loops.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-saturating-arith.ll DAG: Try scalarizing when expanding saturating add/sub 2020-07-16 14:05:16 -04:00
mve-scatter-increment.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
mve-scatter-ind8-unscaled.ll [ARM][MVE] Enable MVE gathers and scatters by default 2020-08-28 19:05:29 +01:00
mve-scatter-ind16-scaled.ll [ARM][MVE] Enable MVE gathers and scatters by default 2020-08-28 19:05:29 +01:00
mve-scatter-ind16-unscaled.ll [ARM][MVE] Enable MVE gathers and scatters by default 2020-08-28 19:05:29 +01:00
mve-scatter-ind32-scaled.ll [ARM][MVE] Enable MVE gathers and scatters by default 2020-08-28 19:05:29 +01:00
mve-scatter-ind32-unscaled.ll [ARM][MVE] Enable MVE gathers and scatters by default 2020-08-28 19:05:29 +01:00
mve-scatter-ptrs.ll [ARM][MVE] Enable MVE gathers and scatters by default 2020-08-28 19:05:29 +01:00
mve-selectcc.ll [ARM] Update target triple in tests. NFC 2020-10-30 15:06:49 +00:00
mve-sext-masked-load.ll [DAGCombiner] Fold sext_inreg of a masked load into a sign extended masked load 2020-07-30 10:34:02 +01:00
mve-sext.ll
mve-shifts-scalar.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-shifts.ll
mve-shuffle.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-shuffleext.ll [ARM] MVE VCVT lowering for f16->f32 extends 2020-06-25 20:54:26 +01:00
mve-shufflemov.ll
mve-simple-arith.ll
mve-soft-float-abi.ll
mve-stack.ll
mve-stacksplot.mir
mve-vabd.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-vaddqr.ll
mve-vaddv.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
mve-vcmp.ll
mve-vcmpf.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-vcmpfr.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-vcmpfz.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-vcmpr.ll
mve-vcmpz.ll
mve-vctp.ll [ARM] Convert VPSEL to VMOV in tail predicated loops 2020-08-03 22:03:14 +01:00
mve-vcvt16.ll [PeepholeOptimizer] Enhance the redundant COPY elimination. 2020-09-22 10:11:37 -04:00
mve-vcvt.ll [ARM] More unpredictable VCVT instructions. 2020-07-21 07:24:37 +01:00
mve-vdup.ll [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend 2020-06-18 13:15:13 +01:00
mve-vecreduce-add.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
mve-vecreduce-addpred.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
mve-vecreduce-bit.ll [ARM] Update target triple in tests. NFC 2020-10-30 15:06:49 +00:00
mve-vecreduce-fadd.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
mve-vecreduce-fminmax.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
mve-vecreduce-fmul.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
mve-vecreduce-loops.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-vecreduce-mla.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
mve-vecreduce-mlapred.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
mve-vecreduce-mul.ll [ARM] Update target triple in tests. NFC 2020-10-30 15:06:49 +00:00
mve-vector-spill.ll Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
mve-vfma.ll
mve-vhaddsub.ll
mve-vld2-post.ll
mve-vld2.ll
mve-vld3.ll
mve-vld4-post.ll
mve-vld4.ll
mve-vldshuffle.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-vldst4.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-vmaxnma-commute.ll [ARM] Mark VMINNMA/VMAXNMA as commutative 2020-08-13 18:01:11 +01:00
mve-vmaxv-vminv-scalar.ll [ARM] Replace llvm.experimental.vector.reduce.smax with llvm.vector.reduce.smax. NFC 2020-10-08 08:05:48 +01:00
mve-vmaxv.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
mve-vmla.ll
mve-vmovimm.ll [ARM] Fix crash trying to generate i1 immediates 2020-06-16 12:27:24 +01:00
mve-vmovn.ll
mve-vmovnstore.ll
mve-vmulh.ll [ARM] Update target triple in tests. NFC 2020-10-30 15:06:49 +00:00
mve-vmull-loop.ll
mve-vmull.ll
mve-vmulqr.ll
mve-vmvnimm.ll
mve-vpsel.ll
mve-vpt-2-blocks-1-pred.mir
mve-vpt-2-blocks-2-preds.mir
mve-vpt-2-blocks-ctrl-flow.mir
mve-vpt-2-blocks-non-consecutive-ins.mir
mve-vpt-2-blocks.mir
mve-vpt-3-blocks-kill-vpr.mir
mve-vpt-block-1-ins.mir
mve-vpt-block-2-ins.mir
mve-vpt-block-4-ins.mir
mve-vpt-block-elses.mir
mve-vpt-block-fold-vcmp.mir
mve-vpt-block-kill.mir [ARM] Remove kill flags between VCMP and insertion point 2020-11-09 13:17:53 +00:00
mve-vpt-block-optnone.mir
mve-vpt-blocks.ll
mve-vpt-from-intrinsics.ll [InstCombine] Move target-specific inst combining 2020-07-22 15:59:49 +02:00
mve-vpt-nots.mir
mve-vpt-optimisations.mir
mve-vpt-preuse.mir
mve-vqdmulh.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
mve-vqmovn-combine.ll [ARM] Update target triple in tests. NFC 2020-10-30 15:06:49 +00:00
mve-vqmovn.ll
mve-vqshrn.ll [ARM] Update target triple in tests. NFC 2020-10-30 15:06:49 +00:00
mve-vst2-post.ll
mve-vst2.ll [ARM] Expand distributing increments to also handle existing pre/post inc instructions. 2020-09-17 16:58:35 +01:00
mve-vst3.ll [MachineInstr] Add support for instructions with multiple memory operands. 2020-11-03 20:44:40 -05:00
mve-vst4-post.ll
mve-vst4.ll
mve-vsubqr.ll
mve-widen-narrow.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-zext-masked-load.ll [DAGCombiner] Fold an AND of a masked load into a zext_masked_load 2020-09-01 17:02:07 +01:00
peephole-addsub.mir
peephole-cmp.mir
pic-load.ll [ARM] Remove more unused check prefixes, NFC 2020-11-14 15:37:53 +00:00
postinc-distribute.mir [ARM] Distribute post-inc for Thumb2 sign/zero extending loads/stores 2020-08-01 14:01:18 +01:00
segmented-stacks.ll
setjmp_longjmp.ll
shift_parts.ll
stack_guard_remat.ll
t2-teq-reduce.mir Rename t2-reduce-size -> thumb2-reduce-size 2020-07-27 13:42:13 -07:00
t2peephole-t2ADDrr-to-t2ADDri.ll
t2sizereduction.mir Rename t2-reduce-size -> thumb2-reduce-size 2020-07-27 13:42:13 -07:00
tail-call-r9.ll
tbb-removeadd.mir
thumb2-adc.ll
thumb2-add2.ll
thumb2-add3.ll
thumb2-add4.ll
thumb2-add5.ll
thumb2-add6.ll
thumb2-add.ll
thumb2-and2.ll
thumb2-and.ll
thumb2-asr2.ll
thumb2-asr.ll
thumb2-bcc.ll
thumb2-bfc.ll
thumb2-bic.ll
thumb2-branch.ll Revert "[BPI] Improve static heuristics for integer comparisons" 2020-08-17 20:44:33 +02:00
thumb2-call-tc.ll
thumb2-call.ll
thumb2-cbnz.ll
thumb2-clz.ll
thumb2-cmn2.ll
thumb2-cmn.ll
thumb2-cmp.ll
thumb2-cpsr-liveness.ll
thumb2-eor2.ll
thumb2-eor.ll
thumb2-execute-only-prologue.ll
thumb2-ifcvt1-tc.ll
thumb2-ifcvt1.ll
thumb2-ifcvt2.ll
thumb2-ifcvt3.ll
thumb2-jtb.ll
thumb2-ldm.ll
thumb2-ldr_ext.ll
thumb2-ldr_post.ll
thumb2-ldr_pre.ll
thumb2-ldr.ll
thumb2-ldrb.ll
thumb2-ldrd.ll
thumb2-ldrh.ll
thumb2-lsl2.ll
thumb2-lsl.ll
thumb2-lsr2.ll
thumb2-lsr3.ll
thumb2-lsr.ll
thumb2-mla.ll
thumb2-mls.ll
thumb2-mov.ll
thumb2-mul.ll
thumb2-mulhi.ll
thumb2-mvn2.ll
thumb2-mvn.ll
thumb2-neg.ll
thumb2-orn2.ll
thumb2-orn.ll
thumb2-orr2.ll
thumb2-orr.ll
thumb2-pack.ll
thumb2-rev16.ll
thumb2-rev.ll
thumb2-ror.ll
thumb2-rsb2.ll
thumb2-rsb.ll
thumb2-sbc.ll
thumb2-select_xform.ll
thumb2-select.ll
thumb2-shifter.ll
thumb2-smla.ll
thumb2-smul.ll
thumb2-spill-q.ll
thumb2-str_post.ll
thumb2-str_pre.ll
thumb2-str.ll
thumb2-strb.ll
thumb2-strh.ll
thumb2-sub2.ll
thumb2-sub3.ll
thumb2-sub4.ll
thumb2-sub5.ll
thumb2-sub.ll
thumb2-sxt_rot.ll
thumb2-sxt-uxt.ll
thumb2-tbb.ll
thumb2-tbh.ll
thumb2-teq2.ll
thumb2-teq.ll
thumb2-tst2.ll
thumb2-tst.ll
thumb2-uxt_rot.ll
thumb2-uxtb.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
tls1.ll
tls2.ll
tpsoft.ll [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
umulo-64-legalisation-lowering.ll
umulo-128-legalisation-lowering.ll [MachineInstr] Add support for instructions with multiple memory operands. 2020-11-03 20:44:40 -05:00
unreachable-large-offset-gep.ll
v8_deprecate_IT.ll
v8_IT_1.ll
v8_IT_2.ll
v8_IT_3.ll
v8_IT_4.ll
v8_IT_5.ll
v8_IT_6.ll
vmovdrroffset.ll [ARM] Fix pointer offset when splitting stores from VMOVDRR 2020-10-03 16:47:50 +01:00
vqabs.ll
vqneg.ll