Matt Arsenault 96e60572ce AMDGPU: Use PatFrags to allow selecting custom nodes or intrinsics ... This enables GlobalISel to handle various intrinsics. The custom node pattern will be ignored, and the intrinsic will work. This will also allow SelectionDAG to directly select the intrinsics, but as they are all custom lowered to the nodes, this ends up leaving dead code in the table. Eventually either GlobalISel should add the equivalent of custom nodes equivalent, or intrinsics should be directly used. These each have different tradeoffs. There are a few more to handle, but these are easy to handle ones. Some others fail for other reasons. llvm-svn: 371432		2019-09-09 18:10:31 +00:00
..
AsmParser	[AMDGPU][MC][GFX10] Corrected constant bus checks to exclude null	2019-09-02 14:19:52 +00:00
Disassembler	[AMDGPU] gfx908 mAI instructions, MC part	2019-07-09 21:43:09 +00:00
MCTargetDesc	[MC] Minor cleanup to MCFixup::Kind handling. NFC.	2019-08-23 01:00:55 +00:00
TargetInfo
Utils	Partially revert D61491 "AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0"	2019-09-02 14:40:57 +00:00
AMDGPU.h	[AMDGPU] Printf runtime binding pass	2019-08-12 17:12:29 +00:00
AMDGPU.td	[AMDGPU] w/a for gfx908 mfma SrcC literal HW bug	2019-08-23 22:09:58 +00:00
AMDGPUAliasAnalysis.cpp	AMDGPU: Improve alias analysis for GDS	2019-07-17 11:22:19 +00:00
AMDGPUAliasAnalysis.h
AMDGPUAlwaysInlinePass.cpp
AMDGPUAnnotateKernelFeatures.cpp	AMDGPU: Add intrinsics for address space identification	2019-09-05 02:20:39 +00:00
AMDGPUAnnotateUniformValues.cpp
AMDGPUArgumentUsageInfo.cpp
AMDGPUArgumentUsageInfo.h	AMDGPU: Fix Register copypaste error	2019-09-05 23:07:10 +00:00
AMDGPUAsmPrinter.cpp	[LLVM][Alignment] Make functions using log of alignment explicit	2019-09-05 10:00:22 +00:00
AMDGPUAsmPrinter.h	[AsmPrinter] Remove const qualifier from EmitBasicBlockStart.	2019-08-20 05:13:57 +00:00
AMDGPUAtomicOptimizer.cpp	[AMDGPU] gfx10 atomic optimizer changes.	2019-08-23 10:07:43 +00:00
AMDGPUCallingConv.td	[AMDGPU] Adjust number of SGPRs available in Calling Convention	2019-08-28 15:00:45 +00:00
AMDGPUCallLowering.cpp	[GlobalISel][CallLowering] Add support for splitting types according to calling conventions.	2019-09-03 21:42:28 +00:00
AMDGPUCallLowering.h	AMDGPU/GlobalISel: Handle most function return types	2019-07-26 02:36:05 +00:00
AMDGPUCodeGenPrepare.cpp	AMDGPU: Preserve value name when inserting mul24 intrinsic	2019-08-24 22:17:10 +00:00
AMDGPUFeatures.td
AMDGPUFixFunctionBitcasts.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUGenRegisterBankInfo.def	[NFC] Fixed -Wdocumentation warning	2019-08-31 18:44:57 +00:00
AMDGPUGISel.td	AMDGPU/GlobalISel: Select atomic loads	2019-09-09 16:18:07 +00:00
AMDGPUHSAMetadataStreamer.cpp	[AMDGPU] Added a new metadata for multi grid sync implicit argument	2019-07-05 16:05:17 +00:00
AMDGPUHSAMetadataStreamer.h	[llvm] Migrate llvm::make_unique to std::make_unique	2019-08-15 15:54:37 +00:00
AMDGPUInline.cpp	[AMDGPU] Tune inlining parameters for AMDGPU target	2019-07-17 16:51:29 +00:00
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td	AMDGPU: Use PatFrags to allow selecting custom nodes or intrinsics	2019-09-09 18:10:31 +00:00
AMDGPUInstructions.td	AMDGPU/GlobalISel: Select local atomic cmpxchg	2019-08-01 03:41:41 +00:00
AMDGPUInstructionSelector.cpp	AMDGPU/GlobalISel: Select G_PTR_MASK	2019-09-09 15:46:13 +00:00
AMDGPUInstructionSelector.h	AMDGPU/GlobalISel: Select G_PTR_MASK	2019-09-09 15:46:13 +00:00
AMDGPUISelDAGToDAG.cpp	Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC	2019-08-01 23:27:28 +00:00
AMDGPUISelLowering.cpp	AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE	2019-09-09 17:13:44 +00:00
AMDGPUISelLowering.h	AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE	2019-09-09 17:13:44 +00:00
AMDGPULegalizerInfo.cpp	AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE	2019-09-09 17:13:44 +00:00
AMDGPULegalizerInfo.h	AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE	2019-09-09 17:13:44 +00:00
AMDGPULibCalls.cpp	Fix missing use of defined() in include guard	2019-07-12 20:12:15 +00:00
AMDGPULibFunc.cpp	[AMDGPU] Downgrade from StringLiteral to const char* in an attempt to make GCC 5 happy	2019-08-25 12:47:31 +00:00
AMDGPULibFunc.h
AMDGPULowerIntrinsics.cpp
AMDGPULowerKernelArguments.cpp
AMDGPULowerKernelAttributes.cpp
AMDGPUMachineCFGStructurizer.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
AMDGPUMachineFunction.cpp	AMDGPU: Make AMDGPUPerfHintAnalysis an SCC pass	2019-07-05 20:26:13 +00:00
AMDGPUMachineFunction.h
AMDGPUMachineModuleInfo.cpp
AMDGPUMachineModuleInfo.h
AMDGPUMacroFusion.cpp
AMDGPUMacroFusion.h
AMDGPUMCInstLower.cpp
AMDGPUOpenCLEnqueuedBlockLowering.cpp	Fix parameter name comments using clang-tidy. NFC.	2019-07-16 04:46:31 +00:00
AMDGPUPerfHintAnalysis.cpp	AMDGPU: Fix assert in clang test	2019-07-05 21:09:53 +00:00
AMDGPUPerfHintAnalysis.h	AMDGPU: Make AMDGPUPerfHintAnalysis an SCC pass	2019-07-05 20:26:13 +00:00
AMDGPUPrintfRuntimeBinding.cpp	Change TargetLibraryInfo analysis passes to always require Function	2019-09-07 03:09:36 +00:00
AMDGPUPromoteAlloca.cpp
AMDGPUPropagateAttributes.cpp	AMDGPU: Move DEBUG_TYPE definition below includes	2019-07-08 18:48:39 +00:00
AMDGPUPTNote.h
AMDGPURegisterBankInfo.cpp	AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE	2019-09-09 17:13:44 +00:00
AMDGPURegisterBankInfo.h	AMDGPU/GlobalISel: Add support for wide loads >= 256-bits	2019-07-10 00:22:41 +00:00
AMDGPURegisterBanks.td	GlobalISel/TableGen: Handle setcc patterns	2019-08-29 01:13:41 +00:00
AMDGPURegisterInfo.cpp	[AMDGPU] gfx908 mAI instructions, MC part	2019-07-09 21:43:09 +00:00
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td	[AMDGPU] gfx908 register file changes	2019-07-09 19:41:51 +00:00
AMDGPURewriteOutArguments.cpp
AMDGPUSearchableTables.td	AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec}	2019-08-05 09:36:06 +00:00
AMDGPUSubtarget.cpp	[AMDGPU] w/a for gfx908 mfma SrcC literal HW bug	2019-08-23 22:09:58 +00:00
AMDGPUSubtarget.h	AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC	2019-09-09 17:04:18 +00:00
AMDGPUTargetMachine.cpp	AMDGPU: Run AMDGPUCodeGenPrepare after scalar opts	2019-08-27 00:08:31 +00:00
AMDGPUTargetMachine.h
AMDGPUTargetObjectFile.cpp
AMDGPUTargetObjectFile.h
AMDGPUTargetTransformInfo.cpp	AMDGPU: Add intrinsics for address space identification	2019-09-05 02:20:39 +00:00
AMDGPUTargetTransformInfo.h	InferAddressSpaces: Move target intrinsic handling to TTI	2019-08-14 18:13:00 +00:00
AMDGPUUnifyDivergentExitNodes.cpp
AMDGPUUnifyMetadata.cpp
AMDILCFGStructurizer.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
AMDKernelCodeT.h
BUFInstructions.td	AMDGPU/GlobalISel: Avoid repeating 32-bit type lists	2019-09-06 00:36:10 +00:00
CaymanInstructions.td
CMakeLists.txt	[AMDGPU] Printf runtime binding pass	2019-08-12 17:12:29 +00:00
DSInstructions.td	AMDGPU: Remove code address space predicates	2019-09-09 16:02:07 +00:00
EvergreenInstructions.td	AMDGPU: Start redefining atomic PatFrags	2019-08-01 03:25:52 +00:00
FLATInstructions.td	AMDGPU/GlobalISel: Avoid repeating 32-bit type lists	2019-09-06 00:36:10 +00:00
GCNDPPCombine.cpp	[AMDGPU] Fix DPP combiner check for exec modification	2019-07-12 15:59:40 +00:00
GCNHazardRecognizer.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
GCNHazardRecognizer.h	[AMDGPU] gfx908 hazard recognizer	2019-07-11 21:30:34 +00:00
GCNILPSched.cpp
GCNIterativeScheduler.cpp	[llvm] Migrate llvm::make_unique to std::make_unique	2019-08-15 15:54:37 +00:00
GCNIterativeScheduler.h
GCNMinRegStrategy.cpp
GCNNSAReassign.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
GCNProcessors.td	[AMDGPU] gfx908 target	2019-07-09 18:10:06 +00:00
GCNRegBankReassign.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
GCNRegPressure.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
GCNRegPressure.h	Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC	2019-08-01 23:27:28 +00:00
GCNSchedStrategy.cpp	AMDGPU: Fix typo	2019-09-06 20:00:22 +00:00
GCNSchedStrategy.h	AMDGPU: Avoid constructing new std::vector in initCandidate	2019-09-05 22:44:06 +00:00
LLVMBuild.txt
MIMGInstructions.td	[AMDGPU] Use PredicateControl in MIMGBaseOpcode. NFC.	2019-08-12 22:32:21 +00:00
R600.td
R600AsmPrinter.cpp	[LLVM][Alignment] Make functions using log of alignment explicit	2019-09-05 10:00:22 +00:00
R600AsmPrinter.h
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
R600FrameLowering.cpp
R600FrameLowering.h
R600InstrFormats.td
R600InstrInfo.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
R600InstrInfo.h
R600Instructions.td	AMDGPU: Redefine load PatFrags	2019-07-16 17:38:50 +00:00
R600ISelLowering.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
R600MachineScheduler.h
R600OpenCLImageTypeLoweringPass.cpp
R600OptimizeVectorRegisters.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
R600Packetizer.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
R600Processors.td
R600RegisterInfo.cpp	Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC	2019-08-01 23:27:28 +00:00
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R700Instructions.td
SIAddIMGInit.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
SIAnnotateControlFlow.cpp
SIDefines.h	[AMDGPU] gfx10 atomic optimizer changes.	2019-08-23 10:07:43 +00:00
SIFixSGPRCopies.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
SIFixupVectorISel.cpp	Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC	2019-08-01 23:27:28 +00:00
SIFixVGPRCopies.cpp
SIFoldOperands.cpp	[AMDGPU] w/a for gfx908 mfma SrcC literal HW bug	2019-08-23 22:09:58 +00:00
SIFormMemoryClauses.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
SIFrameLowering.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
SIFrameLowering.h	[AMDGPU] Add the adjusted FP as a livein register.	2019-07-16 15:57:12 +00:00
SIInsertSkips.cpp
SIInsertWaitcnts.cpp	[llvm] Migrate llvm::make_unique to std::make_unique	2019-08-15 15:54:37 +00:00
SIInstrFormats.td	[AMDGPU] Extend MIMG opcode to 8 bits	2019-07-12 18:38:06 +00:00
SIInstrInfo.cpp	AMDGPU: Allow getMemOperandWithOffset to analyze stack accesses	2019-09-05 23:54:35 +00:00
SIInstrInfo.h	AMDGPU: Don't use frame virtual registers	2019-08-29 01:13:47 +00:00
SIInstrInfo.td	AMDGPU/GlobalISel: Select atomic loads	2019-09-09 16:18:07 +00:00
SIInstructions.td	AMDGPU: Remove pointless wrapper nodes for init.exec intrinsics	2019-09-09 05:49:52 +00:00
SIISelLowering.cpp	AMDGPU: Remove pointless wrapper nodes for init.exec intrinsics	2019-09-09 05:49:52 +00:00
SIISelLowering.h	[LLVM][Alignment] Make functions using log of alignment explicit	2019-09-05 10:00:22 +00:00
SILoadStoreOptimizer.cpp	[AMDGPU] Enable constant offset promotion to immediate operand for VMEM stores	2019-09-06 15:33:53 +00:00
SILowerControlFlow.cpp	Revert "AMDGPU: Fix iterator error when lowering SI_END_CF"	2019-08-20 17:45:25 +00:00
SILowerI1Copies.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
SILowerSGPRSpills.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
SIMachineFunctionInfo.cpp	AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization	2019-08-27 18:18:38 +00:00
SIMachineFunctionInfo.h	AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization	2019-08-27 18:18:38 +00:00
SIMachineScheduler.cpp	[llvm] Migrate llvm::make_unique to std::make_unique	2019-08-15 15:54:37 +00:00
SIMachineScheduler.h
SIMemoryLegalizer.cpp	[llvm] Migrate llvm::make_unique to std::make_unique	2019-08-15 15:54:37 +00:00
SIModeRegister.cpp	[llvm] Migrate llvm::make_unique to std::make_unique	2019-08-15 15:54:37 +00:00
SIOptimizeExecMasking.cpp	Revert "AMDGPU: Fix iterator error when lowering SI_END_CF"	2019-08-20 17:45:25 +00:00
SIOptimizeExecMaskingPreRA.cpp	Revert "AMDGPU: Fix iterator error when lowering SI_END_CF"	2019-08-20 17:45:25 +00:00
SIPeepholeSDWA.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
SIPreAllocateWWMRegs.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
SIProgramInfo.h	[AMDGPU] Fix high occupancy calculation and print it	2019-07-31 01:07:10 +00:00
SIRegisterInfo.cpp	AMDGPU: Handle frame index expansion with no free SGPRs pre gfx9	2019-09-04 17:12:57 +00:00
SIRegisterInfo.h	[AMDGPU] w/a for gfx908 mfma SrcC literal HW bug	2019-08-23 22:09:58 +00:00
SIRegisterInfo.td	AMDGPU/GlobalISel: Avoid repeating 32-bit type lists	2019-09-06 00:36:10 +00:00
SISchedule.td	[AMDGPU] gfx908 scheduling	2019-07-11 21:25:00 +00:00
SIShrinkInstructions.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
SIWholeQuadMode.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
SMInstructions.td	[AMDGPU] Always use s_memtime for readcyclecounter	2019-07-09 03:10:18 +00:00
SOPInstructions.td	[AMDGPU] Mark s_barrier as having side effects but not accessing memory.	2019-09-06 10:07:28 +00:00
VIInstrFormats.td
VIInstructions.td
VOP1Instructions.td	AMDGPU: Move MnemonicAlias out of instruction def hierarchy	2019-09-09 17:25:35 +00:00
VOP2Instructions.td	AMDGPU: Move MnemonicAlias out of instruction def hierarchy	2019-09-09 17:25:35 +00:00
VOP3Instructions.td	AMDGPU: Move MnemonicAlias out of instruction def hierarchy	2019-09-09 17:25:35 +00:00
VOP3PInstructions.td	[AMDGPU] gfx908 mAI instructions, MC part	2019-07-09 21:43:09 +00:00
VOPCInstructions.td	AMDGPU: Redefine setcc condition PatLeafs	2019-07-19 20:24:40 +00:00
VOPInstructions.td	AMDGPU: Move MnemonicAlias out of instruction def hierarchy	2019-09-09 17:25:35 +00:00