Fraser Cormack ba85498148 [RISCV] Fix reporting of incorrect commutable operand indices ... This patch fixes an issue where RISCV's `findCommutedOpIndices` would incorrectly return the pseudo `CommuteAnyOperandIndex` as a commutable operand index, rather than fixing a specific index. Reviewed By: rogfer01 Differential Revision: https://reviews.llvm.org/D108206 (cherry picked from commit 5b06cbac11e53ce55f483c1852a108012507a6bb)		2021-09-03 15:48:26 -07:00
..
AsmParser	[RISCV] Teach constant materialization that it can use zext.w at the end with Zba to reduce number of instructions.	2021-07-16 09:35:56 -07:00
Disassembler	[RISCV] Fix shared libs build	2021-02-09 06:14:25 -06:00
MCTargetDesc	[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.	2021-07-20 09:22:06 -07:00
TargetInfo
CMakeLists.txt	[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.	2021-05-24 11:47:27 -07:00
RISCV.h	[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.	2021-05-24 11:47:27 -07:00
RISCV.td	[RISCV][NFC] Fix formatting	2021-04-09 14:41:09 +08:00
RISCVAsmPrinter.cpp	[RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter.	2021-05-10 09:33:23 +08:00
RISCVCallingConv.td
RISCVCallLowering.cpp	[GlobalISel] Base implementation for sret demotion.	2021-01-06 10:30:50 +05:30
RISCVCallLowering.h	[GlobalISel] Base implementation for sret demotion.	2021-01-06 10:30:50 +05:30
RISCVExpandAtomicPseudoInsts.cpp
RISCVExpandPseudoInsts.cpp	[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.	2021-05-24 11:47:27 -07:00
RISCVFrameLowering.cpp	[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.	2021-07-23 11:35:19 +08:00
RISCVFrameLowering.h	[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.	2021-07-23 11:35:19 +08:00
RISCVInsertVSETVLI.cpp	[RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant.	2021-07-23 09:12:05 -07:00
RISCVInstrFormats.td	[RISCV] Cleanup instruction formats used for B extension ternary operations.	2021-05-06 08:59:05 -07:00
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td	[RISCV] Add new vector instructions in v0.10.	2021-02-03 13:28:58 +08:00
RISCVInstrInfo.cpp	[RISCV] Fix reporting of incorrect commutable operand indices	2021-09-03 15:48:26 -07:00
RISCVInstrInfo.h	[RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.	2021-07-23 11:35:19 +08:00
RISCVInstrInfo.td	[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)	2021-07-20 08:53:55 -07:00
RISCVInstrInfoA.td	[RISCV][NFC] Add explicit type i64 to RV64 only patterns.	2021-04-09 09:37:04 +08:00
RISCVInstrInfoB.td	[RISCV] Optimize multiplication in the zba extension with SH*ADD	2021-07-22 10:28:41 +08:00
RISCVInstrInfoC.td	[RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg.	2021-03-19 20:39:49 -07:00
RISCVInstrInfoD.td	[RISCV] Custom lower (i32 (fptoui/fptosi X)).	2021-07-24 10:50:43 -07:00
RISCVInstrInfoF.td	[RISCV] Custom lower (i32 (fptoui/fptosi X)).	2021-07-24 10:50:43 -07:00
RISCVInstrInfoM.td	[RISCV] Add custom type legalization to form MULHSU when possible.	2021-04-01 10:15:55 -07:00
RISCVInstrInfoV.td	[RISCV] Add scheduling resources for V	2021-08-10 23:11:38 -07:00
RISCVInstrInfoVPseudos.td	[RISCV] Use tail agnostic policy for fixed vector vwmacc(u).	2021-07-16 10:41:09 -07:00
RISCVInstrInfoVSDPatterns.td	[RISCV] Select vector shl by 1 to a vector add.	2021-07-27 10:57:28 -07:00
RISCVInstrInfoVVLPatterns.td	[RISCV] Select vector shl by 1 to a vector add.	2021-07-27 10:57:28 -07:00
RISCVInstrInfoZfh.td	[RISCV] Custom lower (i32 (fptoui/fptosi X)).	2021-07-24 10:50:43 -07:00
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp	[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)	2021-07-20 08:53:55 -07:00
RISCVISelDAGToDAG.h	[RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2)	2021-07-20 08:53:55 -07:00
RISCVISelLowering.cpp	[RISCV] Restrict performANY_EXTENDCombine to prevent an infinite loop.	2021-08-02 11:31:08 -07:00
RISCVISelLowering.h	[RISCV] Add support for vector saturating add/sub operations	2021-07-27 10:04:14 +01:00
RISCVLegalizerInfo.cpp	[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one	2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h	[RISCV] Don't emit save-restore call if function is a interrupt handler	2021-04-16 12:54:47 +08:00
RISCVMCInstLower.cpp	[RISCV] Move instruction information into the RISCVII namespace (NFC)	2021-05-11 16:32:42 -05:00
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp	[RISCV] Reserve an emergency spill slot for any RVV spills	2021-06-03 10:44:34 +01:00
RISCVRegisterInfo.h	[RISCV] Improve register allocation around vector masks	2021-02-20 14:47:51 +00:00
RISCVRegisterInfo.td	[RISCV] Make VLEN no greater than 65536	2021-07-17 12:47:46 +08:00
RISCVSchedRocket.td	[RISCV] Add scheduling resources for V	2021-08-10 23:11:38 -07:00
RISCVSchedSiFive7.td	[RISCV] Add scheduling resources for V	2021-08-10 23:11:38 -07:00
RISCVSchedule.td	[RISCV] Add scheduling resources for V	2021-08-10 23:11:38 -07:00
RISCVScheduleB.td	[RISCV] Move scheduling resources for B into a separate file (NFC)	2021-03-29 20:37:22 -05:00
RISCVScheduleV.td	[RISCV] Add scheduling resources for V	2021-08-10 23:11:38 -07:00
RISCVSubtarget.cpp	[RISCV] Make VLEN no greater than 65536	2021-07-17 12:47:46 +08:00
RISCVSubtarget.h	[RISCV] Don't enable loop vectorizer interleaving if the V extension isn't enabled.	2021-06-07 10:20:59 -07:00
RISCVSystemOperands.td	RISCV: add a few deprecated aliases for CSRs	2021-05-21 13:52:58 -07:00
RISCVTargetMachine.cpp	[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.	2021-05-24 11:47:27 -07:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp	ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects	2021-02-26 16:38:44 -08:00
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp	[RISCV] Teach constant materialization that it can use zext.w at the end with Zba to reduce number of instructions.	2021-07-16 09:35:56 -07:00
RISCVTargetTransformInfo.h	[RISCV] Don't enable Interleaved Access Vectorization	2021-06-18 12:32:30 +08:00