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52358ec746
I found this really weird WWM-related case whereby through the WWM transformations our isel lowering was trying to promote 2 min's into a min3 for the i8 type, which our hardware doesn't support. The new min3_i8.ll test case would previously spew the error: PromoteIntegerResult #0: t69: i8 = SMIN3 t70, Constant:i8<0>, t68 Before the simple fix to our isel lowering to not do it for i8 MVT's. Differential Revision: https://reviews.llvm.org/D59543 llvm-svn: 356464
155 lines
7.0 KiB
LLVM
155 lines
7.0 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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; GCN-LABEL: {{^}}test_fmin3_olt_0_f32:
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; GCN: buffer_load_dword [[REGC:v[0-9]+]]
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; GCN: buffer_load_dword [[REGB:v[0-9]+]]
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; GCN: buffer_load_dword [[REGA:v[0-9]+]]
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; GCN: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; GCN: buffer_store_dword [[RESULT]],
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define amdgpu_kernel void @test_fmin3_olt_0_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 {
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%a = load volatile float, float addrspace(1)* %aptr, align 4
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%b = load volatile float, float addrspace(1)* %bptr, align 4
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%c = load volatile float, float addrspace(1)* %cptr, align 4
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%f0 = call float @llvm.minnum.f32(float %a, float %b)
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%f1 = call float @llvm.minnum.f32(float %f0, float %c)
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store float %f1, float addrspace(1)* %out, align 4
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ret void
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}
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; Commute operand of second fmin
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; GCN-LABEL: {{^}}test_fmin3_olt_1_f32:
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; GCN: buffer_load_dword [[REGB:v[0-9]+]]
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; GCN: buffer_load_dword [[REGA:v[0-9]+]]
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; GCN: buffer_load_dword [[REGC:v[0-9]+]]
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; GCN: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; GCN: buffer_store_dword [[RESULT]],
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define amdgpu_kernel void @test_fmin3_olt_1_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 {
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%a = load volatile float, float addrspace(1)* %aptr, align 4
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%b = load volatile float, float addrspace(1)* %bptr, align 4
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%c = load volatile float, float addrspace(1)* %cptr, align 4
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%f0 = call float @llvm.minnum.f32(float %a, float %b)
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%f1 = call float @llvm.minnum.f32(float %c, float %f0)
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store float %f1, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_fmin3_olt_0_f16:
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; GCN: buffer_load_ushort [[REGC:v[0-9]+]]
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; GCN: buffer_load_ushort [[REGB:v[0-9]+]]
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; GCN: buffer_load_ushort [[REGA:v[0-9]+]]
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; SI: v_min3_f32 [[RESULT_F32:v[0-9]+]],
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; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT]]
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; VI: v_min_f16_e32
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; VI: v_min_f16_e32 [[RESULT:v[0-9]+]],
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; GFX9: v_min3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; GCN: buffer_store_short [[RESULT]],
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define amdgpu_kernel void @test_fmin3_olt_0_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 {
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%a = load volatile half, half addrspace(1)* %aptr, align 2
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%b = load volatile half, half addrspace(1)* %bptr, align 2
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%c = load volatile half, half addrspace(1)* %cptr, align 2
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%f0 = call half @llvm.minnum.f16(half %a, half %b)
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%f1 = call half @llvm.minnum.f16(half %f0, half %c)
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store half %f1, half addrspace(1)* %out, align 2
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ret void
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}
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; Commute operand of second fmin
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; GCN-LABEL: {{^}}test_fmin3_olt_1_f16:
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; GCN: buffer_load_ushort [[REGA:v[0-9]+]]
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; GCN: buffer_load_ushort [[REGB:v[0-9]+]]
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; GCN: buffer_load_ushort [[REGC:v[0-9]+]]
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; SI-DAG: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], [[REGA]]
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; SI-DAG: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], [[REGB]]
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; SI-DAG: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], [[REGC]]
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; SI: v_min3_f32 [[RESULT_F32:v[0-9]+]], [[CVT_C]], [[CVT_A]], [[CVT_B]]
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; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT_F32]]
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; VI: v_min_f16_e32
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; VI: v_min_f16_e32 [[RESULT:v[0-9]+]],
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; GFX9: v_min3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGA]], [[REGB]]
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; GCN: buffer_store_short [[RESULT]],
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define amdgpu_kernel void @test_fmin3_olt_1_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 {
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%a = load volatile half, half addrspace(1)* %aptr, align 2
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%b = load volatile half, half addrspace(1)* %bptr, align 2
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%c = load volatile half, half addrspace(1)* %cptr, align 2
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%f0 = call half @llvm.minnum.f16(half %a, half %b)
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%f1 = call half @llvm.minnum.f16(half %c, half %f0)
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store half %f1, half addrspace(1)* %out, align 2
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ret void
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}
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; Checks whether the test passes; performMinMaxCombine() should not optimize vector patterns of min3
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; since there are no pack instructions for fmin3.
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; GCN-LABEL: {{^}}no_fmin3_v2f16:
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; SI: v_cvt_f16_f32_e32
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; SI: v_min_f32_e32
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; SI-NEXT: v_min_f32_e32
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; SI-NEXT: v_min3_f32
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; SI-NEXT: v_min3_f32
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; VI: s_waitcnt
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; VI-NEXT: v_min_f16_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI-NEXT: v_min_f16_e32 v0, v0, v1
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; VI-NEXT: v_min_f16_sdwa v1, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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; VI-NEXT: v_min_f16_e32 v0, v2, v0
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; VI-NEXT: v_min_f16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
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; VI-NEXT: v_min_f16_e32 v0, v0, v3
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; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; VI-NEXT: s_setpc_b64
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; GFX9: s_waitcnt
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; GFX9-NEXT: v_pk_min_f16 v0, v0, v1
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; GFX9-NEXT: v_pk_min_f16 v0, v2, v0
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; GFX9-NEXT: v_pk_min_f16 v0, v0, v3
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; GFX9-NEXT: s_setpc_b64
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define <2 x half> @no_fmin3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) #2 {
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entry:
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%min = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)
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%min1 = call <2 x half> @llvm.minnum.v2f16(<2 x half> %c, <2 x half> %min)
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%res = call <2 x half> @llvm.minnum.v2f16(<2 x half> %min1, <2 x half> %d)
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ret <2 x half> %res
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}
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; GCN-LABEL: {{^}}test_fmin3_olt_0_f64:
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; GCN-NOT: v_min3
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define amdgpu_kernel void @test_fmin3_olt_0_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %bptr, double addrspace(1)* %cptr) #0 {
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%a = load volatile double, double addrspace(1)* %aptr, align 4
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%b = load volatile double, double addrspace(1)* %bptr, align 4
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%c = load volatile double, double addrspace(1)* %cptr, align 4
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%f0 = call double @llvm.minnum.f64(double %a, double %b)
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%f1 = call double @llvm.minnum.f64(double %f0, double %c)
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store double %f1, double addrspace(1)* %out, align 4
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ret void
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}
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; Commute operand of second fmin
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; GCN-LABEL: {{^}}test_fmin3_olt_1_f64:
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; GCN-NOT: v_min3
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define amdgpu_kernel void @test_fmin3_olt_1_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %bptr, double addrspace(1)* %cptr) #0 {
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%a = load volatile double, double addrspace(1)* %aptr, align 4
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%b = load volatile double, double addrspace(1)* %bptr, align 4
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%c = load volatile double, double addrspace(1)* %cptr, align 4
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%f0 = call double @llvm.minnum.f64(double %a, double %b)
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%f1 = call double @llvm.minnum.f64(double %c, double %f0)
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store double %f1, double addrspace(1)* %out, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare double @llvm.minnum.f64(double, double) #1
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declare float @llvm.minnum.f32(float, float) #1
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declare half @llvm.minnum.f16(half, half) #1
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declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>)
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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attributes #2 = { nounwind "no-nans-fp-math"="true" }
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