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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 20:23:11 +01:00
llvm-mirror/test/CodeGen/AMDGPU
Mark Searles 110a3cbd81 Revert "[AMDGPU] Don’t marke the .note section as ALLOC"
This reverts commit 977cd661cf019039dec7ffdd15bf0ac500828c87.

It breaks OpenCL testing. OpenCL Runtime is using PT_LOAD information
to calculate memory for global variables. This commit should be relanded once
the OpenCL runtime stops relying on PT_LOAD information for calculating global
variable memory size.

Differential Revision: https://reviews.llvm.org/D74995
2020-02-21 16:08:30 -08:00
..
GlobalISel AMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VECTOR on v2i16 2020-02-21 21:16:39 +00:00
32-bit-local-address-space.ll
accvgpr-copy.mir
add3.ll
add_i1.ll
add_i64.ll
add_i128.ll
add_shl.ll
add-debug.ll
add.i16.ll
add.ll
add.v2i16.ll
addrspacecast-captured.ll
addrspacecast-constantexpr.ll
addrspacecast.ll
adjust-writemask-invalid-copy.ll
agpr-register-count.ll
alignbit-pat.ll
alloca.ll
always-uniform.ll
amdgcn-ieee.ll
amdgcn.bitcast.ll AMDGPU: Fix v2i64<->v4f32 bitcast 2020-02-20 09:49:09 -05:00
amdgcn.private-memory.ll
amdgpu-alias-analysis.ll
amdgpu-codegenprepare-fdiv.ll AMDGPU: Enhancement on FDIV lowering in AMDGPUCodeGenPrepare 2020-02-07 11:46:23 -08:00
amdgpu-codegenprepare-fold-binop-select.ll AMDGPU: Use conditions directly in division expansion 2020-02-11 23:11:30 -05:00
amdgpu-codegenprepare-i16-to-i32.ll
amdgpu-codegenprepare-idiv.ll AMDGPU: Enable integer division bypass 2020-02-19 17:50:19 -05:00
amdgpu-codegenprepare-mul24.ll
amdgpu-function-calls-option.ll
amdgpu-inline.ll
amdgpu-mul24-knownbits.ll [AMDGPU] simplifyI24 - replace GetDemandedBits with SimplifyMultipleUseDemandedBits 2020-02-20 12:03:08 +00:00
amdgpu-shader-calling-convention.ll
amdgpu-unroll-threshold.ll
amdgpu.private-memory.ll
amdgpu.work-item-intrinsics.deprecated.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
amdhsa-trap-num-sgprs.ll
amdpal_scratch_mergedshader.ll
amdpal-cs.ll
amdpal-es.ll
amdpal-gs.ll
amdpal-hs.ll
amdpal-ls.ll
amdpal-msgpack-cs.ll
amdpal-msgpack-es.ll
amdpal-msgpack-gs.ll
amdpal-msgpack-hs.ll
amdpal-msgpack-ls.ll
amdpal-msgpack-ps.ll
amdpal-msgpack-psenable.ll
amdpal-msgpack-vs.ll
amdpal-ps.ll
amdpal-psenable.ll
amdpal-vs.ll
amdpal.ll
and_or.ll
and-gcn.ll
and.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
andorbitset.ll
andorn2.ll
andorxorinvimm.ll
annotate-kernel-features-hsa-call.ll
annotate-kernel-features-hsa.ll
annotate-kernel-features.ll
anonymous-gv.ll
any_extend_vector_inreg.ll
anyext.ll
are-loads-from-same-base-ptr.ll
array-ptr-calc-i32.ll
array-ptr-calc-i64.ll
ashr.v2i16.ll [AMDGPU] fixed divergence driven shift operations selection 2020-01-31 20:49:56 +03:00
at-least-one-def-value-assert.mir Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
atomic_cmp_swap_local.ll
atomic_load_add.ll
atomic_load_local.ll
atomic_load_sub.ll
atomic_optimizations_buffer.ll
atomic_optimizations_global_pointer.ll
atomic_optimizations_local_pointer.ll Revert "AMDGPU: Temporary drop s_mul_hi_i/u32 patterns" 2020-01-27 08:07:21 -08:00
atomic_optimizations_pixelshader.ll
atomic_optimizations_raw_buffer.ll
atomic_optimizations_struct_buffer.ll
atomic_store_local.ll
atomicrmw-nand.ll
attr-amdgpu-flat-work-group-size-v3.ll
attr-amdgpu-flat-work-group-size.ll
attr-amdgpu-num-sgpr.ll
attr-amdgpu-num-vgpr.ll
attr-amdgpu-waves-per-eu.ll
attr-unparseable.ll
barrier-elimination.ll
basic-branch.ll
basic-call-return.ll
basic-loop.ll
bfe_uint.ll
bfe-combine.ll
bfe-patterns.ll [AMDGPU] fixed divergence driven shift operations selection 2020-01-31 20:49:56 +03:00
bfi_int.ll
bfm.ll
big_alu.ll
bitcast-constant-to-vector.ll
bitcast-v4f16-v4i16.ll
bitcast-vector-extract.ll
bitreverse-inline-immediates.ll
bitreverse.ll AMDGPU: Use v_perm_b32 to implement bswap 2020-02-13 09:45:31 -08:00
br_cc.f16.ll
branch-condition-and.ll
branch-relax-bundle.ll
branch-relax-spill.ll Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
branch-relaxation-debug-info.ll
branch-relaxation-inst-size-gfx10.ll
branch-relaxation.ll
branch-uniformity.ll
break-smem-soft-clauses.mir
break-vmem-soft-clauses.mir
bswap.ll AMDGPU: Improve i16/v2i16 bswap 2020-02-14 09:53:22 -08:00
buffer-intrinsics-mmo-offsets.ll
buffer-schedule.ll
bug-sdag-scheduler-cycle.ll SelectionDAG: Fix bug in ClusterNeighboringLoads 2020-02-12 09:12:55 +01:00
bug-vopc-commute.ll
build_vector.ll
build-vector-insert-elt-infloop.ll
build-vector-packed-partial-undef.ll
bundle-latency.mir
bypass-div.ll AMDGPU: Enable integer division bypass 2020-02-19 17:50:19 -05:00
byval-frame-setup.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
call_fs.ll
call-argument-types.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
call-constant.ll
call-constexpr.ll
call-encoding.ll
call-graph-register-usage.ll
call-preserved-registers.ll
call-return-types.ll
call-skip.ll
call-to-kernel-undefined.ll Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
call-to-kernel.ll Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
call-waitcnt.ll
call-waw-waitcnt.mir
callee-frame-setup.ll
callee-special-input-sgprs.ll
callee-special-input-vgprs.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
calling-conventions.ll AMDGPU: Allow i16 shader arguments 2020-01-27 06:55:32 -08:00
captured-frame-index.ll
cayman-loop-bug.ll
cc-sgpr-limit.ll
cc-sgpr-over-limit.ll Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
cf_end.ll
cf-loop-on-constant.ll
cf-stack-bug.ll
cgp-addressing-modes-flat.ll
cgp-addressing-modes.ll Reapply "AMDGPU: Cleanup and fix SMRD offset handling" 2020-01-31 06:01:28 -08:00
cgp-bitfield-extract.ll
chain-hi-to-lo.ll AMDGPU: Don't report 2-byte alignment as fast 2020-02-11 18:35:00 -05:00
clamp-modifier.ll [AMDGPU] Fix some tests that did not specify -mcpu 2020-02-17 14:02:32 +00:00
clamp-omod-special-case.mir
clamp.ll
cluster_stores.ll [MachineScheduler] Ignore artificial edges when forming store chains 2020-01-29 16:23:01 +00:00
cluster-flat-loads-postra.mir
cluster-flat-loads.mir
cndmask-no-def-vcc.ll
coalescer_distribute.ll
coalescer_remat.ll
coalescer-extend-pruned-subrange.mir
coalescer-identical-values-undef.mir
coalescer-subranges-another-copymi-not-live.mir
coalescer-subranges-another-prune-error.mir
coalescer-subranges-prune-kill-copy.mir
coalescer-subreg-join.mir
coalescer-subregjoin-fullcopy.mir
coalescer-with-subregs-bad-identical.mir
coalescing-with-subregs-in-loop-bug.mir
code-object-v3.ll
codegen-prepare-addrmode-sext.ll
collapse-endcf2.mir
collapse-endcf-broken.mir
collapse-endcf.ll
collapse-endcf.mir
combine_vloads.ll
combine-and-sext-bool.ll
combine-cond-add-sub.ll
combine-ftrunc.ll
comdat.ll
commute_modifiers.ll
commute-compares.ll
commute-shifts.ll [AMDGPU] fixed divergence driven shift operations selection 2020-01-31 20:49:56 +03:00
complex-folding.ll
computeKnownBits-scalar-to-vector-crash.ll
computeNumSignBits-mul.ll
concat_vectors.ll
constant-address-space-32bit.ll
constant-fold-imm-immreg.mir
constant-fold-mi-operands.ll
control-flow-fastregalloc.ll
control-flow-optnone.ll
convergent-inlineasm.ll
copy-illegal-type.ll [ANDGPU] getMemOperandsWithOffset: support BUF non-stack-access instructions with resource but no vaddr 2020-02-03 22:49:30 +00:00
copy-to-reg.ll
couldnt-join-subrange-3.mir
cross-block-use-is-not-abi-copy.ll
cse-phi-incoming-val.ll
csr-gfx10.ll
ctlz_zero_undef.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
ctlz.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
ctpop16.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
ctpop64.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
ctpop.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
cttz_zero_undef.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
cube.ll
cvt_f32_ubyte.ll [AMDGPU] performCvtF32UByteNCombine - add SHL and SimplifyMultipleUseDemandedBits support 2020-02-19 11:45:57 +00:00
cvt_flr_i32_f32.ll
cvt_rpi_i32_f32.ll
dag-divergence.ll
dagcomb-shuffle-vecextend-non2.ll
dagcombine-reassociate-bug.ll
dagcombine-select.ll AMDGPU: Look through casted selects to constant fold bin ops 2020-01-22 10:16:39 -05:00
dagcombine-setcc-select.ll
dagcombiner-bug-illegal-vec4-int-to-fp.ll
dce-disjoint-intervals.mir
dead_copy.mir
dead-lane.mir
dead-machine-elim-after-dead-lane.ll
debug-value2.ll
debug-value-scheduler-crash.mir
debug-value.ll
debug.ll
default-fp-mode.ll
detect-dead-lanes.mir
directive-amdgcn-target.ll
disable_form_clauses.ll
disconnected-predset-break-bug.ll
div_i128.ll Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
diverge-extra-formal-args.ll
diverge-interp-mov-lower.ll
diverge-switch-default.ll [InstCombine] fix operands of shouldChangeType() for casted phi transform 2020-02-04 07:45:48 -05:00
divergence-at-use.ll
divergent-branch-uniform-condition.ll
divrem24-assume.ll [AMDGPU] Fix some tests that did not specify -mcpu 2020-02-17 14:02:32 +00:00
dpp_combine.ll
dpp_combine.mir
drop-mem-operand-move-smrd.ll
ds_read2_offset_order.ll AMDGPU/SILoadStoreOptimizer: Improve merging of out of order offsets 2020-01-24 19:45:56 -08:00
ds_read2_superreg.ll
ds_read2.ll
ds_read2st64.ll
ds_write2.ll
ds_write2st64.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
ds-combine-large-stride.ll
ds-combine-with-dependence.ll
ds-negative-offset-addressing-mode-loop.ll
ds-sub-offset.ll
dynamic_stackalloc.ll
early-if-convert-cost.ll
early-if-convert.ll
early-inline-alias.ll
early-inline.ll
early-tailduplicator-nophis.mir
elf-header-flags-mach.ll
elf-header-flags-sram-ecc.ll
elf-header-flags-xnack.ll
elf-header-osabi.ll
elf-notes.ll
elf.ll
elf.metadata.ll
elf.r600.ll
else.ll
empty-function.ll
enable-no-signed-zeros-fp-math.ll
endcf-loop-header.ll
endpgm-dce.mir
enqueue-kernel.ll
exceed-max-sgprs.ll
extend-bit-ops-i16.ll
extload-align.ll
extload-private.ll
extload.ll
extract_subvector_vec4_vec3.ll
extract_vector_dynelt.ll
extract_vector_elt-f16.ll
extract_vector_elt-f64.ll
extract_vector_elt-i8.ll
extract_vector_elt-i16.ll
extract_vector_elt-i64.ll
extract-lowbits.ll [AMDGPU] fixed divergence driven shift operations selection 2020-01-31 20:49:56 +03:00
extract-subvector-equal-length.ll
extract-subvector.ll
extract-vector-elt-build-vector-combine.ll
extractelt-to-trunc.ll [DAGCombine] visitEXTRACT_VECTOR_ELT - add SimplifyDemandedBits multi use support 2020-02-20 15:49:38 +00:00
fabs.f16.ll
fabs.f64.ll
fabs.ll
fadd64.ll
fadd-fma-fmul-combine.ll [AMDGPU] Fix some tests that did not specify -mcpu 2020-02-17 14:02:32 +00:00
fadd.f16.ll
fadd.ll
fast-unaligned-load-store.global.ll AMDGPU: Don't report 2-byte alignment as fast 2020-02-11 18:35:00 -05:00
fast-unaligned-load-store.private.ll AMDGPU: Don't report 2-byte alignment as fast 2020-02-11 18:35:00 -05:00
fcanonicalize-elimination.ll [NFC] Fix check prefix add in fcanonicalize-elimination.ll 2020-01-30 17:19:49 -05:00
fcanonicalize.f16.ll
fcanonicalize.ll
fceil64.ll
fceil.ll
fcmp64.ll
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.f16.ll
fcmp.ll
fconst64.ll
fcopysign.f16.ll
fcopysign.f32.ll
fcopysign.f64.ll
fdiv32-to-rcp-folding.ll AMDGPU: Implement FDIV optimizations in AMDGPUCodeGenPrepare 2020-01-23 16:57:43 -08:00
fdiv.f16.ll AMDGPU: Enhancement on FDIV lowering in AMDGPUCodeGenPrepare 2020-02-07 11:46:23 -08:00
fdiv.f64.ll
fdiv.ll AMDGPU: Implement FDIV optimizations in AMDGPUCodeGenPrepare 2020-01-23 16:57:43 -08:00
fdot2.ll
fence-barrier.ll
fetch-limits.r600.ll
fetch-limits.r700+.ll
fexp.ll
ffloor.f64.ll
ffloor.ll
fix-sgpr-copies.mir
fix-vgpr-copies.mir
fix-wwm-vgpr-copy.ll
flat_atomics_i64.ll
flat_atomics.ll
flat-address-space.ll
flat-error-unsupported-gpu-hsa.ll Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
flat-for-global-subtarget-feature.ll
flat-load-clustering.mir
flat-offset-bug.ll
flat-scratch-reg.ll
floor.ll
fma-combine.ll [AMDGPU] Fix infinite loop with fma combines 2020-02-04 13:11:09 -08:00
fma.f64.ll
fma.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
fmac.sdwa.ll
fmad.ll
fmax3.f64.ll
fmax3.ll
fmax_legacy.f16.ll
fmax_legacy.f64.ll
fmax_legacy.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
fmax.ll
fmaxnum.f64.ll
fmaxnum.ll
fmaxnum.r600.ll
fmed3.ll
fmin3.ll
fmin_fmax_legacy.amdgcn.ll
fmin_legacy.f16.ll
fmin_legacy.f64.ll
fmin_legacy.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
fmin.ll
fminnum.f64.ll
fminnum.ll
fminnum.r600.ll
fmul64.ll
fmul-2-combine-multi-use.ll
fmul.f16.ll
fmul.ll
fmuladd.f16.ll
fmuladd.f32.ll
fmuladd.f64.ll
fmuladd.v2f16.ll
fnearbyint.ll
fneg-combines.ll [AMDGPU] Fix infinite loop with fma combines 2020-02-04 13:11:09 -08:00
fneg-combines.si.ll
fneg-fabs.f16.ll
fneg-fabs.f64.ll
fneg-fabs.ll
fneg-fold-legalize-dag-increase-insts.ll
fneg.f16.ll
fneg.f64.ll
fneg.ll
fold_acc_copy_into_valu.mir
fold-cndmask.mir
fold-fi-mubuf.mir
fold-fi-operand-shrink.mir
fold-fmul-to-neg-abs.ll
fold-imm-copy.mir
fold-imm-f16-f32.mir
fold-immediate-operand-shrink-with-carry.mir
fold-immediate-operand-shrink.mir
fold-immediate-output-mods.mir
fold-implicit-operand.mir
fold-multiple.mir
fold-operands-order.mir
fold-operands-remove-m0-redef.mir
fold-over-exec.mir
fold-readlane.mir
fold-reload-into-m0.mir
fold-sgpr-copy.mir
fold-sgpr-multi-imm.mir
fold-vgpr-copy.mir
force-alwaysinline-lds-global-address-codegen.ll
force-alwaysinline-lds-global-address.ll
fp16_to_fp32.ll
fp16_to_fp64.ll
fp32_to_fp16.ll
fp_to_sint.f64.ll
fp_to_sint.ll
fp_to_uint.f64.ll
fp_to_uint.ll
fp-atomic-to-s_denormmode.mir
fp-classify.ll
fpext-free.ll
fpext.f16.ll
fpext.ll
fpow.ll
fptosi.f16.ll
fptoui.f16.ll
fptrunc.f16.ll
fptrunc.ll
fract.f64.ll
fract.ll
frame-index-elimination.ll
frame-lowering-entry-all-sgpr-used.mir
frame-lowering-fp-adjusted.mir
frem.ll [AMDGPU] Fix some tests that did not specify -mcpu 2020-02-17 14:02:32 +00:00
fsqrt.f64.ll
fsqrt.ll AMDGPU/EG,CM: Implement fsqrt using recip(rsqrt(x)) instead of x * rsqrt(x) 2020-02-05 00:24:07 -05:00
fsub64.ll
fsub.f16.ll
fsub.ll
ftrunc.f64.ll
ftrunc.ll
function-args.ll
function-call-relocs.ll
function-returns.ll
gds-atomic.ll
gep-address-space.ll
gfx10-vop-literal.ll
gfx902-without-xnack.ll
global_atomics_i64.ll
global_atomics.ll
global_smrd_cfg.ll
global_smrd.ll
global-atomics-fp.ll
global-constant.ll AMDGPU/R600: Emit rodata in text segment 2020-01-22 14:31:51 -05:00
global-directive.ll
global-extload-i16.ll
global-load-store-atomics.mir
global-saddr.ll [AMDGPU] Cluster FLAT instructions with both vaddr and saddr 2020-01-29 17:01:35 +00:00
global-smrd-unknown.ll
global-variable-relocs.ll
gv-const-addrspace.ll
gv-offset-folding.ll
gws-hazards.mir
half.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
hazard-buffer-store-v-interp.mir
hazard-hidden-bundle.mir
hazard-in-bundle.mir
hazard-inlineasm.mir
hazard-kill.mir
hazard.mir
hoist-cond.ll
hsa-default-device.ll
hsa-fp-mode.ll
hsa-func-align.ll
hsa-func.ll
hsa-globals.ll
hsa-group-segment.ll
hsa-metadata-deduce-ro-arg-v3.ll
hsa-metadata-deduce-ro-arg.ll
hsa-metadata-enqueue-kernel-v3.ll
hsa-metadata-enqueue-kernel.ll
hsa-metadata-from-llvm-ir-full-v3.ll
hsa-metadata-from-llvm-ir-full.ll
hsa-metadata-hidden-args-v3.ll
hsa-metadata-hidden-args.ll
hsa-metadata-hostcall-absent-v3.ll
hsa-metadata-hostcall-absent.ll
hsa-metadata-hostcall-present-v3.ll
hsa-metadata-hostcall-present.ll
hsa-metadata-images-v3.ll
hsa-metadata-images.ll
hsa-metadata-invalid-ocl-version-1-v3.ll
hsa-metadata-invalid-ocl-version-1.ll
hsa-metadata-invalid-ocl-version-2-v3.ll
hsa-metadata-invalid-ocl-version-2.ll
hsa-metadata-invalid-ocl-version-3-v3.ll
hsa-metadata-invalid-ocl-version-3.ll
hsa-metadata-kernel-code-props-v3.ll
hsa-metadata-kernel-code-props.ll
hsa-metadata-wavefrontsize.ll
hsa-note-no-func.ll
hsa.ll Revert "[AMDGPU] Don’t marke the .note section as ALLOC" 2020-02-21 16:08:30 -08:00
huge-private-buffer.ll
i1_copy_phi_with_phi_incoming_value.mir
i1-copies-rpo.mir
i1-copy-from-loop.ll AMDGPU: Switch some tests to use generated checks 2020-01-31 20:29:41 -05:00
i1-copy-implicit-def.ll
i1-copy-phi-uniform-branch.ll
i1-copy-phi.ll
i8-to-double-to-float.ll
icmp64.ll
icmp-select-sete-reverse-args.ll
icmp.i16.ll
idiv-licm.ll
idot2.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
idot4s.ll [DAGCombine] visitEXTRACT_VECTOR_ELT - add SimplifyDemandedBits multi use support 2020-02-20 15:49:38 +00:00
idot4u.ll [DAGCombine] visitEXTRACT_VECTOR_ELT - add SimplifyDemandedBits multi use support 2020-02-20 15:49:38 +00:00
idot8s.ll [DAGCombine] visitEXTRACT_VECTOR_ELT - add SimplifyDemandedBits multi use support 2020-02-20 15:49:38 +00:00
idot8u.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
illegal-sgpr-to-vgpr-copy.ll
image_ls_mipmap_zero.ll
image-attributes.ll
image-load-d16-tfe.ll
image-resource-id.ll
image-schedule.ll
img-nouse-adjust.ll
imm16.ll [AMDGPU] Regenerate immediate constant tests 2020-02-19 18:58:44 +00:00
imm.ll [AMDGPU] Regenerate immediate constant tests 2020-02-19 18:58:44 +00:00
immv216.ll
implicit-def-muse.ll
indirect-addressing-si-gfx9.ll
indirect-addressing-si-noopt.ll
indirect-addressing-si-pregfx9.ll
indirect-addressing-si.ll
indirect-addressing-term.ll
indirect-private-64.ll
infer-addrpace-pipeline.ll
infinite-loop-evergreen.ll
infinite-loop.ll
inline-asm.ll AMDGPU: Analyze divergence of inline asm 2020-02-03 12:42:16 -08:00
inline-attr.ll
inline-calls.ll
inline-constraints.ll
inline-maxbb.ll
inlineasm-16.ll
inlineasm-illegal-type.ll
inlineasm-packed.ll
InlineAsmCrash.ll
input-mods.ll
insert_subreg.ll
insert_vector_dynelt.ll
insert_vector_elt.ll [ANDGPU] getMemOperandsWithOffset: support BUF non-stack-access instructions with resource but no vaddr 2020-02-03 22:49:30 +00:00
insert_vector_elt.v2i16.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
insert_vector_elt.v2i16.subtest-nosaddr.ll
insert_vector_elt.v2i16.subtest-saddr.ll
insert-skip-from-vcc.mir
insert-skips-flat-vmem.mir
insert-skips-gws.mir
insert-skips-ignored-insts.mir
insert-skips-kill-uncond.mir
insert-subvector-unused-scratch.ll
insert-waitcnts-callee.mir
insert-waitcnts-exp.mir
inserted-wait-states.mir
internalize.ll
invalid-addrspacecast.ll
invalid-alloca.ll
invariant-load-no-alias-store.ll
invert-br-undef-vcc.mir
ipra-regmask.ll
ipra.ll
jump-address.ll
kcache-fold.ll
kernarg-stack-alignment.ll
kernel-args.ll
kernel-argument-dag-lowering.ll AMDGPU: Fix crash on v3i15 kernel arguments 2020-02-11 18:11:39 -05:00
kill-infinite-loop.ll AMDGPU: Fix AMDGPUUnifyDivergentExitNodes with no normal returns 2020-01-30 10:55:02 +01:00
known-never-nan.ll
known-never-snan.ll AMDGPU: Implement FDIV optimizations in AMDGPUCodeGenPrepare 2020-01-23 16:57:43 -08:00
knownbits-recursion.ll
large-alloca-compute.ll
large-alloca-graphics.ll
large-constant-initializer.ll
large-work-group-promote-alloca.ll
lcssa-optnone.ll
lds_atomic_f32.ll
lds-alignment.ll
lds-bounds.ll
lds-branch-vmem-hazard.mir
lds-global-non-entry-func.ll
lds-initializer.ll Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
lds-m0-init-in-loop.ll
lds-misaligned-bug.ll
lds-oqap-crash.ll
lds-output-queue.ll
lds-relocs.ll AMDGPU/GlobalISel: Handle LDS with relocations case 2020-01-29 08:18:55 -08:00
lds-size.ll
lds-zero-initializer.ll Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
legalize-fp-load-invariant.ll
legalizedag-bug-expand-setcc.ll
limit-coalesce.mir
lit.local.cfg
literals.ll
liveness.mir
llvm.amdgcn.alignb.ll
llvm.amdgcn.atomic.dec.ll
llvm.amdgcn.atomic.fadd.ll
llvm.amdgcn.atomic.inc.ll
llvm.amdgcn.buffer.atomic.ll
llvm.amdgcn.buffer.load.dwordx3.ll
llvm.amdgcn.buffer.load.format.d16.ll
llvm.amdgcn.buffer.load.format.ll
llvm.amdgcn.buffer.load.ll
llvm.amdgcn.buffer.store.dwordx3.ll
llvm.amdgcn.buffer.store.format.d16.ll
llvm.amdgcn.buffer.store.format.ll
llvm.amdgcn.buffer.store.ll
llvm.amdgcn.buffer.wbinvl1.ll
llvm.amdgcn.buffer.wbinvl1.sc.ll
llvm.amdgcn.buffer.wbinvl1.vol.ll
llvm.amdgcn.class.f16.ll
llvm.amdgcn.class.ll
llvm.amdgcn.cos.f16.ll
llvm.amdgcn.cos.ll
llvm.amdgcn.cubeid.ll
llvm.amdgcn.cubema.ll
llvm.amdgcn.cubesc.ll
llvm.amdgcn.cubetc.ll
llvm.amdgcn.cvt.pk.i16.ll
llvm.amdgcn.cvt.pk.u16.ll
llvm.amdgcn.cvt.pknorm.i16.ll
llvm.amdgcn.cvt.pknorm.u16.ll
llvm.amdgcn.cvt.pkrtz.ll
llvm.amdgcn.dispatch.id.ll
llvm.amdgcn.dispatch.ptr.ll
llvm.amdgcn.div.fixup.f16.ll
llvm.amdgcn.div.fixup.ll
llvm.amdgcn.div.fmas.ll
llvm.amdgcn.div.scale.ll
llvm.amdgcn.ds.append.ll
llvm.amdgcn.ds.bpermute.ll
llvm.amdgcn.ds.consume.ll
llvm.amdgcn.ds.gws.barrier.ll
llvm.amdgcn.ds.gws.init.ll
llvm.amdgcn.ds.gws.sema.br.ll
llvm.amdgcn.ds.gws.sema.p.ll
llvm.amdgcn.ds.gws.sema.release.all.ll Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
llvm.amdgcn.ds.gws.sema.v.ll
llvm.amdgcn.ds.ordered.add.gfx10.ll
llvm.amdgcn.ds.ordered.add.ll AMDGPU: Don't error on ds.ordered intrinsic in function 2020-01-24 13:06:44 -08:00
llvm.amdgcn.ds.ordered.swap.ll
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll
llvm.amdgcn.exp.compr.ll
llvm.amdgcn.exp.ll
llvm.amdgcn.exp.prim.ll
llvm.amdgcn.fcmp.ll
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fdot2.ll
llvm.amdgcn.fmad.ftz.f16.ll
llvm.amdgcn.fmad.ftz.ll
llvm.amdgcn.fmed3.f16.ll
llvm.amdgcn.fmed3.ll
llvm.amdgcn.fmul.legacy.ll
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll
llvm.amdgcn.frexp.exp.f16.ll
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll
llvm.amdgcn.icmp.ll
llvm.amdgcn.image.a16.dim.ll [AMDGPU] Add a16 feature to gfx10 2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.a16.encode.ll [AMDGPU] Add a16 feature to gfx10 2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.atomic.dim.ll
llvm.amdgcn.image.d16.dim.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.dim.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.gather4.a16.dim.ll [AMDGPU] Add a16 feature to gfx10 2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.gather4.d16.dim.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.gather4.dim.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.gather4.o.dim.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.getlod.dim.ll
llvm.amdgcn.image.load.a16.d16.ll [AMDGPU] Add a16 feature to gfx10 2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.load.a16.ll [AMDGPU] Add a16 feature to gfx10 2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.nsa.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.sample.a16.dim.ll [AMDGPU] Add a16 feature to gfx10 2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.sample.d16.dim.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.sample.dim.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.sample.ltolz.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.sample.o.dim.ll [AMDGPU] Use v3f32 type in image instructions 2020-02-05 10:35:41 +01:00
llvm.amdgcn.image.store.a16.d16.ll [AMDGPU] Add a16 feature to gfx10 2020-02-10 09:04:23 +01:00
llvm.amdgcn.image.store.a16.ll [AMDGPU] Add a16 feature to gfx10 2020-02-10 09:04:23 +01:00
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
llvm.amdgcn.implicit.buffer.ptr.ll
llvm.amdgcn.implicitarg.ptr.ll
llvm.amdgcn.init.exec.ll
llvm.amdgcn.init.exec.wave32.ll
llvm.amdgcn.interp.f16.ll
llvm.amdgcn.interp.ll
llvm.amdgcn.is.private.ll
llvm.amdgcn.is.shared.ll
llvm.amdgcn.kernarg.segment.ptr.ll
llvm.amdgcn.kill.ll
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll
llvm.amdgcn.log.clamp.ll
llvm.amdgcn.mbcnt.ll
llvm.amdgcn.mfma.ll
llvm.amdgcn.mov.dpp8.ll
llvm.amdgcn.mov.dpp.ll
llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll
llvm.amdgcn.mul.i24.ll
llvm.amdgcn.mul.u24.ll
llvm.amdgcn.permlane.ll AMDGPU/GlobalISel: Select permlane16/permlanex16 2020-01-29 17:55:31 -05:00
llvm.amdgcn.ps.live.ll
llvm.amdgcn.qsad.pk.u16.u8.ll
llvm.amdgcn.queue.ptr.ll
llvm.amdgcn.raw.buffer.atomic.ll
llvm.amdgcn.raw.buffer.load.format.d16.ll
llvm.amdgcn.raw.buffer.load.format.ll
llvm.amdgcn.raw.buffer.load.ll
llvm.amdgcn.raw.buffer.store.format.d16.ll
llvm.amdgcn.raw.buffer.store.format.ll
llvm.amdgcn.raw.buffer.store.ll
llvm.amdgcn.raw.tbuffer.load.d16.ll
llvm.amdgcn.raw.tbuffer.load.ll
llvm.amdgcn.raw.tbuffer.store.d16.ll
llvm.amdgcn.raw.tbuffer.store.ll
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll AMDGPU: Implement FDIV optimizations in AMDGPUCodeGenPrepare 2020-01-23 16:57:43 -08:00
llvm.amdgcn.readfirstlane.ll
llvm.amdgcn.readlane.ll
llvm.amdgcn.rsq.clamp.ll
llvm.amdgcn.rsq.f16.ll
llvm.amdgcn.rsq.legacy.ll
llvm.amdgcn.rsq.ll
llvm.amdgcn.s.barrier.ll
llvm.amdgcn.s.buffer.load.ll Reapply "AMDGPU: Cleanup and fix SMRD offset handling" 2020-01-31 06:01:28 -08:00
llvm.amdgcn.s.dcache.inv.ll
llvm.amdgcn.s.dcache.inv.vol.ll
llvm.amdgcn.s.dcache.wb.ll
llvm.amdgcn.s.dcache.wb.vol.ll
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.get.waveid.in.workgroup.ll
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll
llvm.amdgcn.s.memtime.ll [AMDGPU] Fix some tests that did not specify -mcpu 2020-02-17 14:02:32 +00:00
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll
llvm.amdgcn.sad.hi.u8.ll
llvm.amdgcn.sad.u8.ll
llvm.amdgcn.sad.u16.ll
llvm.amdgcn.sbfe.ll
llvm.amdgcn.sdot2.ll
llvm.amdgcn.sdot4.ll
llvm.amdgcn.sdot8.ll
llvm.amdgcn.sendmsg.ll
llvm.amdgcn.set.inactive.ll
llvm.amdgcn.sffbh.ll
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll
llvm.amdgcn.softwqm.ll
llvm.amdgcn.struct.buffer.atomic.ll
llvm.amdgcn.struct.buffer.load.format.d16.ll
llvm.amdgcn.struct.buffer.load.format.ll
llvm.amdgcn.struct.buffer.load.ll
llvm.amdgcn.struct.buffer.store.format.d16.ll
llvm.amdgcn.struct.buffer.store.format.ll
llvm.amdgcn.struct.buffer.store.ll
llvm.amdgcn.struct.tbuffer.load.d16.ll
llvm.amdgcn.struct.tbuffer.load.ll
llvm.amdgcn.struct.tbuffer.store.d16.ll
llvm.amdgcn.struct.tbuffer.store.ll
llvm.amdgcn.tbuffer.load.d16.ll
llvm.amdgcn.tbuffer.load.dwordx3.ll
llvm.amdgcn.tbuffer.load.ll
llvm.amdgcn.tbuffer.store.d16.ll
llvm.amdgcn.tbuffer.store.dwordx3.ll
llvm.amdgcn.tbuffer.store.ll
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll
llvm.amdgcn.udot2.ll
llvm.amdgcn.udot4.ll
llvm.amdgcn.udot8.ll
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll
llvm.amdgcn.wave.barrier.ll
llvm.amdgcn.wavefrontsize.ll
llvm.amdgcn.workgroup.id.ll
llvm.amdgcn.workitem.id.ll
llvm.amdgcn.wqm.vote.ll
llvm.amdgcn.writelane.ll
llvm.ceil.f16.ll
llvm.cos.f16.ll AMDGPU: Fix not using f16 fsin/fcos 2020-01-27 08:59:59 -08:00
llvm.cos.ll
llvm.dbg.value.ll
llvm.exp2.f16.ll
llvm.exp2.ll
llvm.floor.f16.ll
llvm.fma.f16.ll
llvm.fmuladd.f16.ll
llvm.log2.f16.ll
llvm.log2.ll
llvm.log10.f16.ll
llvm.log10.ll
llvm.log.f16.ll
llvm.log.ll
llvm.maxnum.f16.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
llvm.memcpy.ll [ANDGPU] getMemOperandsWithOffset: support BUF non-stack-access instructions with resource but no vaddr 2020-02-03 22:49:30 +00:00
llvm.minnum.f16.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
llvm.pow.ll
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.f64.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
llvm.round.ll
llvm.sin.f16.ll AMDGPU: Fix not using f16 fsin/fcos 2020-01-27 08:59:59 -08:00
llvm.sin.ll
llvm.sqrt.f16.ll
llvm.trunc.f16.ll
load-constant-f32.ll
load-constant-f64.ll
load-constant-i1.ll
load-constant-i8.ll
load-constant-i16.ll
load-constant-i32.ll
load-constant-i64.ll
load-global-f32.ll
load-global-f64.ll
load-global-i1.ll
load-global-i8.ll
load-global-i16.ll
load-global-i32.ll
load-global-i64.ll
load-hi16.ll
load-input-fold.ll
load-lo16.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
load-local-f32-no-ds128.ll
load-local-f32.ll
load-local-f64.ll
load-local-i1.ll
load-local-i8.ll
load-local-i16.ll
load-local-i32.ll
load-local-i64.ll
load-select-ptr.ll
load-weird-sizes.ll
local-64.ll
local-atomics64.ll
local-atomics-fp.ll
local-atomics.ll
local-memory.amdgcn.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
local-memory.ll
local-memory.r600.ll
local-stack-slot-offset.ll
loop_break.ll AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break 2020-02-03 07:02:05 -08:00
loop_exit_with_xor.ll
loop_header_nopred.mir
loop-address.ll
loop-idiom.ll
lower-kernargs.ll
lower-mem-intrinsics-threshold.ll AMDGPU: Add flag to control mem intrinsic expansion 2020-02-03 14:26:01 -08:00
lower-mem-intrinsics.ll AMDGPU: Use generated checks for memcpy expansion 2020-02-14 15:57:40 -08:00
lower-range-metadata-intrinsic-call.ll
lshl64-to-32.ll [AMDGPU] simplifyI24 - replace GetDemandedBits with SimplifyMultipleUseDemandedBits 2020-02-20 12:03:08 +00:00
lshr.v2i16.ll [AMDGPU] fixed divergence driven shift operations selection 2020-01-31 20:49:56 +03:00
macro-fusion-cluster-vcc-uses.mir
mad24-get-global-id.ll
mad_64_32.ll
mad_int24.ll
mad_uint24.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
mad-combine.ll
mad-mix-hi.ll
mad-mix-lo.ll
mad-mix.ll
mad.u16.ll
madak-inline-constant.mir
madak.ll
madmk.ll [AMDGPU] Fix some tests that did not specify -mcpu 2020-02-17 14:02:32 +00:00
mai-hazards.mir
mai-inline.ll
max3.ll
max-literals.ll
max-sgprs.ll
max.i16.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
max.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
mcp-overlap-after-propagation.mir [AMDGPU] Add a16 feature to gfx10 2020-02-10 09:04:23 +01:00
med3-no-simplify.ll
mem-builtins.ll
memcpy-inline-fails.ll Update tests for @llvm.memcpy.inline intrinsics 2020-01-28 10:32:43 +01:00
memory_clause.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
memory_clause.mir
memory-legalizer-amdpal.ll
memory-legalizer-atomic-cmpxchg.ll
memory-legalizer-atomic-fence.ll
memory-legalizer-atomic-insert-end.mir
memory-legalizer-atomic-rmw.ll
memory-legalizer-invalid-addrspace.mir
memory-legalizer-invalid-syncscope.ll
memory-legalizer-load.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
memory-legalizer-local.mir
memory-legalizer-mesa3d.ll
memory-legalizer-multiple-mem-operands-atomics.mir
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
memory-legalizer-region.mir
memory-legalizer-store-infinite-loop.ll
memory-legalizer-store.ll
merge-image-load.mir
merge-image-sample.mir
merge-load-store-physreg.mir
merge-load-store-vreg.mir
merge-load-store.mir AMDGPU/SILoadStoreOptimizer: Improve merging of out of order offsets 2020-01-24 19:45:56 -08:00
merge-m0.mir
merge-store-crash.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
merge-store-usedef.ll
merge-stores.ll [ANDGPU] getMemOperandsWithOffset: support BUF non-stack-access instructions with resource but no vaddr 2020-02-03 22:49:30 +00:00
merge-tbuffer.mir AMDGPU/SILoadStoreOptimizer: Improve merging of out of order offsets 2020-01-24 19:45:56 -08:00
mesa3d.ll
mesa_regression.ll
mfma-loop.ll
min3.ll
min.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
mir-print-dead-csr-fi.mir
misched-killflags.mir
missing-store.ll
mixed_wave32_wave64.ll
mixed-wave32-wave64.ll
mode-register.mir
move-addr64-rsrc-dead-subreg-writes.ll
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll
movreld-bug.ll
movrels-bug.mir
mubuf-legalize-operands.ll
mubuf-legalize-operands.mir
mubuf-offset-private.ll
mubuf-shader-vgpr.ll
mubuf.ll
mul24-pass-ordering.ll AMDGPU: Implement FDIV optimizations in AMDGPUCodeGenPrepare 2020-01-23 16:57:43 -08:00
mul_int24.ll
mul_uint24-amdgcn.ll
mul_uint24-r600.ll
mul.i16.ll
mul.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
multi-divergent-exit-region.ll
multi-dword-vgpr-spill.ll
multilevel-break.ll AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break 2020-02-03 07:02:05 -08:00
nand.ll
nested-calls.ll
nested-loop-conditions.ll AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break 2020-02-03 07:02:05 -08:00
no-hsa-graphics-shaders.ll
no-initializer-constant-addrspace.ll
no-remat-indirect-mov.mir
no-shrink-extloads.ll
noop-shader-O0.ll
nop-data.ll
nop-fold.mir
nor.ll
not-scalarize-volatile-load.ll
nsa-reassign.ll
nsa-vmem-hazard.mir [AMDGPU] Add a16 feature to gfx10 2020-02-10 09:04:23 +01:00
nullptr.ll
occupancy-levels.ll
offset-split-flat.ll
offset-split-global.ll
omod-nsz-flag.mir AMDGPU: Split denormal mode tracking bits 2020-02-04 10:44:21 -08:00
omod.ll [AMDGPU] Fix some tests that did not specify -mcpu 2020-02-17 14:02:32 +00:00
opencl-image-metadata.ll
opencl-printf-no-hostcall.ll
opencl-printf.ll
operand-folding.ll [AMDGPU] Fix some tests that did not specify -mcpu 2020-02-17 14:02:32 +00:00
operand-spacing.ll
opt-sgpr-to-vgpr-copy.mir
optimize-exec-masking-pre-ra.mir
optimize-if-exec-masking.mir
optimize-negated-cond-exec-masking-wave32.mir
optimize-negated-cond-exec-masking.mir
optimize-negated-cond.ll
or3.ll
or.ll
pack.v2f16.ll
pack.v2i16.ll
packed-op-sel.ll
packetizer.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll
partial-shift-shrink.ll
partially-dead-super-register-immediate.ll
peephole-opt-regseq-removal.mir
pei-reg-scavenger-position.mir
pei-scavenge-sgpr-carry-out.mir
pei-scavenge-sgpr-gfx9.mir
pei-scavenge-sgpr.mir
perfhint.ll
permute.ll
phi-elimination-assertion.mir
phi-elimination-end-cf.mir
pk_max_f16_literal.ll
post-ra-sched-kill-bundle-use-inst.mir
postra-bundle-memops.mir [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
postra-machine-sink.mir
postra-norename.mir
power-sched-no-instr-sunit.mir
predicate-dp4.ll
predicates.ll
preserve-hi16.ll
print-mir-custom-pseudo.ll
private-access-no-objects.ll
private-element-size.ll
private-memory-atomics.ll
private-memory-r600.ll
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll
promote-alloca-calling-conv.ll
promote-alloca-globals.ll
promote-alloca-invariant-markers.ll
promote-alloca-lifetime.ll
promote-alloca-mem-intrinsics.ll
promote-alloca-no-opts.ll
promote-alloca-padding-size-estimate.ll
promote-alloca-stored-pointer-value.ll
promote-alloca-to-lds-icmp.ll
promote-alloca-to-lds-phi.ll
promote-alloca-to-lds-select.ll
promote-alloca-unhandled-intrinsic.ll
promote-alloca-vector-to-vector.ll
promote-alloca-volatile.ll
promote-constOffset-to-imm-gfx10.mir
promote-constOffset-to-imm.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
promote-constOffset-to-imm.mir
propagate-attributes-bitcast-function.ll
propagate-attributes-clone.ll
propagate-attributes-single-set.ll
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll R600: Fix failing testcase 2020-01-22 16:01:35 -05:00
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.add.ll
r600.alu-limits.ll
r600.amdgpu-alias-analysis.ll
r600.bitcast.ll Regenerate bitcast test for upcoming patch. 2020-02-02 18:27:44 +00:00
r600.extract-lowbits.ll
r600.func-alignment.ll
r600.global_atomics.ll
r600.private-memory.ll
r600.sub.ll
r600.work-item-intrinsics.ll
r600cfg.ll
rcp_iflag.ll AMDGPU: Implement FDIV optimizations in AMDGPUCodeGenPrepare 2020-01-23 16:57:43 -08:00
rcp-pattern.ll AMDGPU: Implement FDIV optimizations in AMDGPUCodeGenPrepare 2020-01-23 16:57:43 -08:00
read_register.ll
read-register-invalid-subtarget.ll Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
read-register-invalid-type-i32.ll Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
read-register-invalid-type-i64.ll Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
readcyclecounter.ll
readlane_exec0.mir
README
reassoc-scalar.ll
reduce-build-vec-ext-to-ext-build-vec.ll
reduce-load-width-alignment.ll
reduce-saveexec.mir
reduce-store-width-alignment.ll
reduction.ll
reg-coalescer-sched-crash.ll
regbank-reassign.mir
regcoal-subrange-join-seg.mir
regcoal-subrange-join.mir
regcoalesce-cannot-join-failures.mir
regcoalesce-dbg.mir
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
regcoalesce-prune.mir
regcoalescing-remove-partial-redundancy-assert.mir
register-count-comments.ll
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir
rename-independent-subregs.mir
reorder-stores.ll
reqd-work-group-size.ll [InstCombine] fix operands of shouldChangeType() for casted phi transform 2020-02-04 07:45:48 -05:00
ret_jump.ll
ret.ll
returnaddress.ll
rewrite-out-arguments-address-space.ll
rewrite-out-arguments.ll
rotl.i64.ll
rotl.ll
rotr.i64.ll
rotr.ll
rsq.ll AMDGPU: Implement FDIV optimizations in AMDGPUCodeGenPrepare 2020-01-23 16:57:43 -08:00
rv7x0_count3.ll
s_addk_i32.ll
s_code_end.ll
s_movk_i32.ll
s_mulk_i32.ll
sad.ll
saddo.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
salu-to-valu.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
sampler-resource-id.ll
scalar_to_vector_v2x16.ll
scalar_to_vector.ll [SelectionDAG] Optimize build_vector of truncates and shifts 2020-02-10 15:04:07 +01:00
scalar-branch-missing-and-exec.ll
scalar-store-cache-flush.mir
sched-assert-dead-def-subreg-use-other-subreg.mir
sched-assert-onlydbg-value-empty-region.mir
sched-crash-dbg-value.mir
sched-handleMoveUp-subreg-def-across-subreg-def.mir
schedule-barrier.mir
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll
schedule-if-2.ll
schedule-if.ll
schedule-ilp.ll
schedule-kernel-arg-loads.ll
schedule-regpressure-limit2.ll
schedule-regpressure-limit3.ll
schedule-regpressure-limit-clustering.ll [AMDGPU] Attempt to reschedule withou clustering 2020-01-27 10:27:16 -08:00
schedule-regpressure-limit.ll
schedule-regpressure.mir
schedule-vs-if-nested-loop-failure.ll
schedule-vs-if-nested-loop.ll
scheduler-handle-move-bundle.mir
scheduler-subrange-crash.ll
scratch-buffer.ll
scratch-simple.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
sdiv64.ll AMDGPU: Enable integer division bypass 2020-02-19 17:50:19 -05:00
sdiv.ll [AMDGPU] Fix some tests that did not specify -mcpu 2020-02-17 14:02:32 +00:00
sdivrem24.ll
sdivrem64.r600.ll AMDGPU: Enable integer division bypass 2020-02-19 17:50:19 -05:00
sdwa-gfx9.mir
sdwa-op64-test.ll
sdwa-ops.mir
sdwa-peephole-instr-gfx10.mir
sdwa-peephole-instr.mir
sdwa-peephole.ll
sdwa-preserve.mir
sdwa-scalar-ops.mir [AMDGPU] Fixed subreg use in sdwa-scalar-ops.mir. NFC 2020-02-11 14:27:17 -08:00
sdwa-vop2-64bit.mir
select64.ll
select-fabs-fneg-extract-legacy.ll
select-fabs-fneg-extract.ll AMDGPU: Do binop of select of constant fold in AMDGPUCodeGenPrepare 2020-01-22 10:16:39 -05:00
select-i1.ll
select-opt.ll
select-undef.ll
select-vectors.ll
select.f16.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
sendmsg-m0-hazard.mir
set-dx10.ll
setcc64.ll
setcc-equivalent.ll
setcc-fneg-constant.ll
setcc-limit-load-shrink.ll
setcc-opt.ll
setcc-sext.ll
setcc.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
seto.ll
setuo.ll
sext-eliminate.ll
sext-in-reg-failure-r600.ll
sext-in-reg.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
sgpr-control-flow.ll AMDGPU: Switch some tests to use generated checks 2020-01-31 20:29:41 -05:00
sgpr-copy-duplicate-operand.ll
sgpr-copy.ll
sgpr-spill-wrong-stack-id.mir
sgprcopies.ll
shader-addr64-nonuniform.ll
shared-op-cycle.ll
shift-and-i64-ubfe.ll
shift-and-i128-ubfe.ll
shift-i64-opts.ll
shift-i128.ll
shift-select.ll [AMDGPU] fixed divergence driven shift operations selection 2020-01-31 20:49:56 +03:00
shl_add_constant.ll
shl_add_ptr.ll
shl_add.ll
shl_or.ll
shl-add-to-add-shl.ll
shl.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
shl.v2i16.ll [AMDGPU] fixed divergence driven shift operations selection 2020-01-31 20:49:56 +03:00
shrink-add-sub-constant.ll
shrink-carry.mir
shrink-vop3-carry-out.mir
si-annotate-cf-noloop.ll
si-annotate-cf-unreachable.ll
si-annotate-cf.ll
si-annotate-cfg-loop-assert.ll
si-annotatecfg-multiple-backedges.ll AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break 2020-02-03 07:02:05 -08:00
si-fix-sgpr-copies.mir
si-i1-copies.mir
si-if-lower-user-terminators.mir AMDGPU: Fix SI_IF lowering when the save exec reg has terminator uses 2020-02-09 17:59:19 -05:00
si-instr-info-correct-implicit-operands.ll
si-lower-control-flow-kill.ll
si-lower-control-flow-unreachable-block.ll
si-lower-control-flow.mir
si-lower-i1-copies.mir
si-lower-sgpr-spills.mir
si-scheduler.ll
si-sgpr-spill.ll
si-spill-cf.ll
si-spill-sgpr-stack.ll
si-triv-disjoint-mem-access.ll [AMDGPU] Cluster FLAT instructions with both vaddr and saddr 2020-01-29 17:01:35 +00:00
si-vector-hang.ll
sibling-call.ll
sign_extend.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
simplify-libcalls.ll
simplifydemandedbits-recursion.ll
sint_to_fp.f64.ll
sint_to_fp.i64.ll
sint_to_fp.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
sitofp.f16.ll
skip-branch-taildup-ret.mir
skip-branch-trap.ll
skip-if-dead.ll test/CodeGen/AMDGPU: Add a test case that shows a miscompilation 2020-02-21 13:38:24 +01:00
smed3.ll
smem-no-clause-coalesced.mir
smem-war-hazard.mir
sminmax.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
sminmax.v2i16.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
smrd_vmem_war.ll
smrd-fold-offset.mir
smrd-gfx10.ll
smrd-vccz-bug.ll
smrd.ll AMDGPU: Fix splitting wide f32 s.buffer.load intrinsics 2020-02-03 12:28:08 -08:00
sopk-compares.ll
sp-too-many-input-sgprs.ll
speculative-execution-freecasts.ll SpeculativeExecution: fixed ingoring free execution 2020-02-20 14:45:02 +03:00
spill-agpr.ll
spill-alloc-sgpr-init-bug.ll
spill-before-exec.mir
spill-cfg-position.ll
spill-csr-frame-ptr-reg-copy.ll
spill-empty-live-interval.mir
spill-m0.ll
spill-offset-calculation.ll
spill-scavenge-offset.ll
spill-vgpr-to-agpr.ll
spill-wide-sgpr.ll
split-arg-dbg-value.ll
split-scalar-i64-add.ll
split-smrd.ll
split-vector-memoperand-offsets.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
splitkit.mir
sra.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
sram-ecc-default.ll
srem64.ll AMDGPU: Enable integer division bypass 2020-02-19 17:50:19 -05:00
srem.ll
srl.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
ssubo.ll
stack-pointer-offset-relative-frameindex.ll
stack-realign-kernel.ll
stack-realign.ll
stack-size-overflow.ll
stack-slot-color-sgpr-vgpr-spills.mir
store_typed.ll
store-barrier.ll
store-global.ll
store-hi16.ll
store-local.ll
store-private.ll
store-v3i64.ll
store-vector-ptrs.ll
store-weird-sizes.ll [DAGCombine] visitEXTRACT_VECTOR_ELT - add SimplifyDemandedBits multi use support 2020-02-20 15:49:38 +00:00
stress-calls.ll
structurize1.ll
structurize.ll
sub_i1.ll
sub-zext-cc-zext-cc.ll
sub.i16.ll
sub.ll
sub.v2i16.ll
subreg_interference.mir
subreg-coalescer-crash.ll
subreg-coalescer-undef-use.ll
subreg-eliminate-dead.ll
subreg-intervals.mir
subreg-split-live-in-error.mir
subreg-undef-def-with-other-subreg-defs.mir
subvector-test.mir
swizzle-export.ll
syncscopes.ll
tail-call-cgp.ll
tail-dup-bundle.mir
tail-duplication-convergent.ll
target-cpu.ll
tex-clause-antidep.ll
texture-input-merge.ll
trap.ll
trunc-bitcast-vector.ll
trunc-cmp-constant.ll
trunc-combine.ll
trunc-store-f64-to-f16.ll
trunc-store-i1.ll
trunc-store.ll
trunc-vector-store-assertion-failure.ll
trunc.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
tti-unroll-prefs.ll
twoaddr-fma.mir
twoaddr-mad.mir
uaddo.ll
udiv64.ll AMDGPU: Enable integer division bypass 2020-02-19 17:50:19 -05:00
udiv.ll
udivrem24.ll
udivrem64.r600.ll
udivrem.ll
uint_to_fp.f64.ll
uint_to_fp.i64.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
uint_to_fp.ll AMDGPU: Move R600 test compatability hack 2020-02-10 10:02:06 -08:00
uitofp.f16.ll
umed3.ll
unaligned-load-store.ll AMDGPU: Don't report 2-byte alignment as fast 2020-02-11 18:35:00 -05:00
undefined-physreg-sgpr-spill.mir
undefined-subreg-liverange.ll
unhandled-loop-condition-assertion.ll
uniform-branch-intrinsic-cond.ll
uniform-cfg.ll
uniform-crash.ll
uniform-loop-inside-nonuniform.ll
uniform-work-group-attribute-missing.ll
uniform-work-group-nested-function-calls.ll
uniform-work-group-prevent-attribute-propagation.ll
uniform-work-group-propagate-attribute.ll
uniform-work-group-recursion-test.ll
uniform-work-group-test.ll
unify-metadata.ll
unigine-liveness-crash.ll
unknown-processor.ll
unpack-half.ll
unroll.ll
unsupported-calls.ll
unsupported-cc.ll
unsupported-image-a16.ll Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
update-phi.ll AMDGPU: Fix AMDGPUUnifyDivergentExitNodes with no normal returns 2020-01-30 10:55:02 +01:00
urem64.ll AMDGPU: Enable integer division bypass 2020-02-19 17:50:19 -05:00
urem.ll
use-sgpr-multiple-times.ll
usubo.ll
v1i64-kernel-arg.ll
v1024.ll
v_cndmask.ll
v_cvt_pk_u8_f32.ll
v_mac_f16.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
v_mac.ll [AMDGPU] Fix some tests that did not specify -mcpu 2020-02-17 14:02:32 +00:00
v_madak_f16.ll [AMDGPU] Bundle loads before post-RA scheduler 2020-01-24 11:33:38 -08:00
v_swap_b32.mir AMDGPU: Limit the search in finding the instruction pattern for v_swap generation. 2020-02-07 11:06:33 -08:00
valu-i1.ll
vccz-corrupt-bug-workaround.mir [AMDGPU] Fix vccz after v_readlane/v_readfirstlane to vcc_lo/hi 2020-01-28 10:52:17 +00:00
vcmpx-exec-war-hazard.mir
vcmpx-permlane-hazard.mir
vector_shuffle.packed.ll [SelectionDAG] Optimize build_vector of truncates and shifts 2020-02-10 15:04:07 +01:00
vector-alloca-addrspacecast.ll
vector-alloca-atomic.ll
vector-alloca.ll
vector-extract-insert.ll
vector-legalizer-divergence.ll
vectorize-buffer-fat-pointer.ll
vectorize-global-local.ll
verify-sop.mir Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
vertex-fetch-encoding.ll
vgpr-descriptor-waterfall-loop-idom-update.ll
vgpr-spill-emergency-stack-slot-compute.ll
vgpr-spill-emergency-stack-slot.ll
vi-removed-intrinsics.ll
virtregrewrite-undef-identity-copy.mir
vmem-to-salu-hazard.mir
vmem-vcc-hazard.mir
vop-shrink-frame-index.mir
vop-shrink-non-ssa.mir
vop-shrink.ll
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll
waitcnt-back-edge-loop.mir
waitcnt-debug.mir
waitcnt-flat.ll
waitcnt-loop-irreducible.mir
waitcnt-loop-single-basic-block.mir
waitcnt-looptest.ll
waitcnt-no-redundant.mir
waitcnt-overflow.mir
waitcnt-permute.mir
waitcnt-preexisting.mir
waitcnt-vscnt.ll
waitcnt-vscnt.mir
waitcnt.mir
wave32.ll
wave_dispatch_regs.ll
widen_extending_scalar_loads.ll
widen-smrd-loads.ll
widen-vselect-and-mask.ll
wqm.ll
wqm.mir
write_register.ll
write-register-vgpr-into-sgpr.ll
wrong-transalu-pos-fix.ll
wwm-reserved.ll
xfail.r600.bitcast.ll
xnor.ll
xor3-i1-const.ll
xor3.ll
xor_add.ll
xor.ll
zero_extend.ll
zext-i64-bit-operand.ll
zext-lid.ll

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.