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https://github.com/RPCS3/llvm-mirror.git
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0e8face627
Now we have vec3 MVTs, this commit implements dwordx3 variants of the buffer intrinsics. On gfx6, a dwordx3 buffer load intrinsic is implemented as a dwordx4 instruction, and a dwordx3 buffer store intrinsic is not supported. We need to support the dwordx3 load intrinsic because it is generated by subtarget-unaware code in InstCombine. Differential Revision: https://reviews.llvm.org/D58904 Change-Id: I016729d8557b98a52f529638ae97c340a5922a4e llvm-svn: 356755
54 lines
2.4 KiB
LLVM
54 lines
2.4 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
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;CHECK-LABEL: {{^}}buffer_store_format_immoffs_x3:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_format_xyz v[0:2], off, s[0:3], 0 offset:42
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define amdgpu_ps void @buffer_store_format_immoffs_x3(<4 x i32> inreg, <3 x float>) {
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main_body:
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call void @llvm.amdgcn.buffer.store.format.v3f32(<3 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_store_immoffs_x3:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 offset:42
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define amdgpu_ps void @buffer_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {
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main_body:
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call void @llvm.amdgcn.buffer.store.v3f32(<3 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
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ret void
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}
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;CHECK-LABEL: {{^}}raw_buffer_store_format_immoffs_x3:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_format_xyz v[0:2], off, s[0:3], 0 offset:42
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define amdgpu_ps void @raw_buffer_store_format_immoffs_x3(<4 x i32> inreg, <3 x float>) {
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main_body:
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call void @llvm.amdgcn.raw.buffer.store.format.v3f32(<3 x float> %1, <4 x i32> %0, i32 42, i32 0, i32 0)
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ret void
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}
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;CHECK-LABEL: {{^}}raw_buffer_store_immoffs_x3:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 offset:42
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define amdgpu_ps void @raw_buffer_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {
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main_body:
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call void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float> %1, <4 x i32> %0, i32 42, i32 0, i32 0)
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ret void
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}
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;CHECK-LABEL: {{^}}struct_buffer_store_immoffs_x3:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_store_dwordx3 v[0:2], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
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define amdgpu_ps void @struct_buffer_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {
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main_body:
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call void @llvm.amdgcn.struct.buffer.store.v3f32(<3 x float> %1, <4 x i32> %0, i32 0, i32 42, i32 0, i32 0)
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ret void
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}
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declare void @llvm.amdgcn.buffer.store.v3f32(<3 x float>, <4 x i32>, i32, i32, i1, i1) #0
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declare void @llvm.amdgcn.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i1, i1) #0
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declare void @llvm.amdgcn.raw.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i32) #0
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declare void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float>, <4 x i32>, i32, i32, i32) #0
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declare void @llvm.amdgcn.struct.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i32, i32) #0
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declare void @llvm.amdgcn.struct.buffer.store.v3f32(<3 x float>, <4 x i32>, i32, i32, i32, i32) #0
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