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53 lines
3.6 KiB
LLVM
53 lines
3.6 KiB
LLVM
; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rv710 | FileCheck %s
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; CHECK: TEX 9 @6 ; encoding: [0x06,0x00,0x00,0x00,0x00,0x04,0x88,0x80]
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define amdgpu_vs void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
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bb:
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%tmp = extractelement <4 x float> %reg1, i32 0
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%tmp1 = extractelement <4 x float> %reg1, i32 1
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%tmp2 = extractelement <4 x float> %reg1, i32 2
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%tmp3 = extractelement <4 x float> %reg1, i32 3
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%tmp4 = insertelement <4 x float> undef, float %tmp, i32 0
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%tmp5 = insertelement <4 x float> %tmp4, float %tmp1, i32 1
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%tmp6 = insertelement <4 x float> %tmp5, float %tmp2, i32 2
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%tmp7 = insertelement <4 x float> %tmp6, float %tmp3, i32 3
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%tmp8 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp9 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1)
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%tmp10 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp11 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp10, i32 0, i32 0, i32 0, i32 1, i32 0, i32 1, i32 1, i32 1, i32 1)
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%tmp12 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp13 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp12, i32 0, i32 0, i32 0, i32 2, i32 0, i32 1, i32 1, i32 1, i32 1)
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%tmp14 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp15 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp14, i32 0, i32 0, i32 0, i32 3, i32 0, i32 1, i32 1, i32 1, i32 1)
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%tmp16 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp17 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp16, i32 0, i32 0, i32 0, i32 4, i32 0, i32 1, i32 1, i32 1, i32 1)
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%tmp18 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp19 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp18, i32 0, i32 0, i32 0, i32 5, i32 0, i32 1, i32 1, i32 1, i32 1)
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%tmp20 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp21 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp20, i32 0, i32 0, i32 0, i32 6, i32 0, i32 1, i32 1, i32 1, i32 1)
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%tmp22 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp23 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp22, i32 0, i32 0, i32 0, i32 7, i32 0, i32 1, i32 1, i32 1, i32 1)
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%tmp24 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp25 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp24, i32 0, i32 0, i32 0, i32 8, i32 0, i32 1, i32 1, i32 1, i32 1)
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%tmp26 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp27 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp26, i32 0, i32 0, i32 0, i32 9, i32 0, i32 1, i32 1, i32 1, i32 1)
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%tmp28 = fadd <4 x float> %tmp9, %tmp11
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%tmp29 = fadd <4 x float> %tmp28, %tmp13
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%tmp30 = fadd <4 x float> %tmp29, %tmp15
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%tmp31 = fadd <4 x float> %tmp30, %tmp17
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%tmp32 = fadd <4 x float> %tmp31, %tmp19
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%tmp33 = fadd <4 x float> %tmp32, %tmp21
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%tmp34 = fadd <4 x float> %tmp33, %tmp23
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%tmp35 = fadd <4 x float> %tmp34, %tmp25
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%tmp36 = fadd <4 x float> %tmp35, %tmp27
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call void @llvm.r600.store.swizzle(<4 x float> %tmp36, i32 0, i32 2)
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ret void
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}
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declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0
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attributes #0 = { nounwind readnone }
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