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llvm-mirror/test
Cullen Rhodes 1ae2c0fb16 [AArch64][SME] Add zero instruction
This patch adds the zero instruction for zeroing a list of 64-bit
element ZA tiles. The instruction takes a list of up to eight tiles
ZA0.D-ZA7.D, which must be in order, e.g.

  zero {za0.d,za1.d,za2.d,za3.d,za4.d,za5.d,za6.d,za7.d}
  zero {za1.d,za3.d,za5.d,za7.d}

The assembler also accepts 32-bit, 16-bit and 8-bit element tiles which
are mapped to corresponding 64-bit element tiles in accordance with the
architecturally defined mapping between different element size tiles,
e.g.

  * Zeroing ZA0.B, or the entire array name ZA, is equivalent to zeroing
    all eight 64-bit element tiles ZA0.D to ZA7.D.
  * Zeroing ZA0.S is equivalent to zeroing ZA0.D and ZA4.D.

The preferred disassembly of this instruction uses the shortest list of
tile names that represent the encoded immediate mask, e.g.

  * An immediate which encodes 64-bit element tiles ZA0.D, ZA1.D, ZA4.D and
    ZA5.D is disassembled as {ZA0.S, ZA1.S}.
  * An immediate which encodes 64-bit element tiles ZA0.D, ZA2.D, ZA4.D and
    ZA6.D is disassembled as {ZA0.H}.
  * An all-ones immediate is disassembled as {ZA}.
  * An all-zeros immediate is disassembled as an empty list {}.

This patch adds the MatrixTileList asm operand and related parsing to support
this.

Depends on D105570.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D105575
2021-07-27 08:35:45 +00:00
..
Analysis [Analysis] Fix getOrderedReductionCost to call target's getArithmeticInstrCost implementation 2021-07-26 17:15:43 +01:00
Assembler
Bindings
Bitcode [IR] Rename comdat noduplicates to comdat nodeduplicate 2021-07-20 12:47:10 -07:00
BugPoint
CodeGen [ARM] Implement isLoad/StoreFromStackSlot for MVE stack stores accesses 2021-07-27 09:11:58 +01:00
DebugInfo [CodeView] Saturate values bigger than supported by APInt. 2021-07-26 22:15:26 +02:00
Demangle
Examples
ExecutionEngine [JITLink][RISCV] Run new test from 0ad562b48 only if the RISCV backend is enabled 2021-07-25 10:47:26 -04:00
Feature
FileCheck
Instrumentation [hwasan] Use stack safety analysis. 2021-07-22 16:20:27 -07:00
Integer
JitListener
Linker [IR] Rename comdat noduplicates to comdat nodeduplicate 2021-07-20 12:47:10 -07:00
LTO [LTO] Add SelectionKind to IRSymtab and use it in ld.lld/LLVMgold 2021-07-20 13:22:00 -07:00
MachineVerifier [MachineVerifier] Make INSERT_SUBREG diagnostic respect operand 2 subregs 2021-07-21 08:47:17 -07:00
MC [AArch64][SME] Add zero instruction 2021-07-27 08:35:45 +00:00
Object [llvm-readobj] Display multiple function names for stack size entries 2021-07-26 14:49:53 +01:00
ObjectYAML [yaml2obj][MachO] Rename PayloadString to Content 2021-07-26 09:04:51 -07:00
Other [ConstantFold] Fix GEP of GEP fold with opaque pointers 2021-07-23 23:56:41 +02:00
SafepointIRVerifier
Support
SymbolRewriter [IR] Rename comdat noduplicates to comdat nodeduplicate 2021-07-20 12:47:10 -07:00
TableGen
ThinLTO/X86 Revert "ThinLTO: Fix inline assembly references to static functions with CFI" 2021-07-20 13:59:46 -07:00
tools [Debug-Info][llvm-dwarfdump] Don't try to dump location 2021-07-27 07:28:59 +00:00
Transforms [LoopFlatten] Use SCEV and Loop APIs to identify increment and trip count 2021-07-27 08:42:59 +01:00
Unit
Verifier [Verifier] Check byval/etc type when comparing ABI attributes 2021-07-20 20:19:47 +02:00
YAMLParser
.clang-format
CMakeLists.txt [test] Add llvm-stress to LLVM_TEST_DEPENDS and lit substitutions 2021-07-22 09:37:01 -07:00
lit.cfg.py [test] Add llvm-stress to LLVM_TEST_DEPENDS and lit substitutions 2021-07-22 09:37:01 -07:00
lit.site.cfg.py.in
TestRunner.sh