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llvm-mirror/utils/TableGen
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Simon Tatham cd2724a625 [TableGen:AsmWriter] Cope with consecutive tied operands. 
When you define an instruction alias as a subclass of InstAlias, you
specify all the MC operands for the instruction it expands to, except
for operands that are tied to a previous one, which you leave out in
the expectation that the Tablegen output code will fill them in
automatically.

But the code in Tablegen's AsmWriter backend that skips over a tied
operand was doing it using 'if' instead of 'while', because it wasn't
expecting to find two tied operands in sequence.

So if an instruction updates a pair of registers in place, so that its
MC representation has two input operands tied to the output ones (for
example, Arm's UMLAL instruction), then any alias which wants to
expand to a special case of that instruction is likely to fail to
match, because the indices of subsequent operands will be off by one
in the generated printAliasInstr function.

This patch re-indents some existing code, so it's clearest when
viewed as a diff with whitespace changes ignored.

Reviewers: fhahn, rengolin, sdesmalen, atanasyan, asb, jholewinski, t.p.northover, kparzysz, craig.topper, stoklund

Reviewed By: rengolin

Subscribers: javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D53816

llvm-svn: 349141
2018-12-14 11:39:55 +00:00
..
AsmMatcherEmitter.cpp Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFC 2018-10-19 06:12:02 +00:00
AsmWriterEmitter.cpp [TableGen:AsmWriter] Cope with consecutive tied operands. 2018-12-14 11:39:55 +00:00
AsmWriterInst.cpp
AsmWriterInst.h
Attributes.cpp
CallingConvEmitter.cpp
CMakeLists.txt [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel. 2018-10-25 07:44:01 +00:00
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp [TableGen] Preserve order of output operands in DAGISelMatcherGen 2018-12-05 00:47:59 +00:00
CodeGenDAGPatterns.h [TableGen] Preserve order of output operands in DAGISelMatcherGen 2018-12-05 00:47:59 +00:00
CodeGenHwModes.cpp
CodeGenHwModes.h
CodeGenInstruction.cpp [ARM][MC] Move information about variadic register defs into tablegen 2018-12-03 10:32:42 +00:00
CodeGenInstruction.h [ARM][MC] Move information about variadic register defs into tablegen 2018-12-03 10:32:42 +00:00
CodeGenIntrinsics.h Mark @llvm.trap cold 2018-11-14 19:53:41 +00:00
CodeGenMapTable.cpp
CodeGenRegisters.cpp [TableGen] Examine entire subreg compositions to detect ambiguity 2018-11-29 18:20:08 +00:00
CodeGenRegisters.h [TableGen] Return ValueTypeByHwMode by const reference from CodeGenRegisterClass::getValueTypeNum 2018-08-16 15:29:24 +00:00
CodeGenSchedule.cpp [llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666). 2018-11-29 12:15:56 +00:00
CodeGenSchedule.h [llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666). 2018-11-29 12:15:56 +00:00
CodeGenTarget.cpp Mark @llvm.trap cold 2018-11-14 19:53:41 +00:00
CodeGenTarget.h [GlobalISel][Tablegen] Assign small opcodes to pseudos 2018-05-23 22:10:21 +00:00
CTagsEmitter.cpp llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) 2018-09-27 02:13:45 +00:00
DAGISelEmitter.cpp [TableGen] Support multi-alternative pattern fragments 2018-07-13 13:18:00 +00:00
DAGISelMatcher.cpp TableGen/ISel: Allow PatFrag predicate code to access captured operands 2018-11-30 14:15:13 +00:00
DAGISelMatcher.h TableGen/ISel: Allow PatFrag predicate code to access captured operands 2018-11-30 14:15:13 +00:00
DAGISelMatcherEmitter.cpp TableGen/ISel: Allow PatFrag predicate code to access captured operands 2018-11-30 14:15:13 +00:00
DAGISelMatcherGen.cpp [TableGen] Preserve order of output operands in DAGISelMatcherGen 2018-12-05 00:47:59 +00:00
DAGISelMatcherOpt.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
DFAPacketizerEmitter.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
DisassemblerEmitter.cpp [WebAssembly] Initial Disassembler. 2018-05-10 22:16:44 +00:00
ExegesisEmitter.cpp [llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target. 2018-11-09 13:15:32 +00:00
FastISelEmitter.cpp TableGen/ISel: Allow PatFrag predicate code to access captured operands 2018-11-30 14:15:13 +00:00
FixedLenDecoderEmitter.cpp Recommit r349041: [tblgen][disasm] Separate encodings from instructions 2018-12-13 16:17:54 +00:00
GlobalISelEmitter.cpp TableGen/ISel: Allow PatFrag predicate code to access captured operands 2018-11-30 14:15:13 +00:00
InfoByHwMode.cpp llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) 2018-09-27 02:13:45 +00:00
InfoByHwMode.h [TableGen] Don't separately search for DefaultMode when we're going to iterate the set anyway. NFCI. 2018-08-17 17:45:15 +00:00
InstrDocsEmitter.cpp [ARM][MC] Move information about variadic register defs into tablegen 2018-12-03 10:32:42 +00:00
InstrInfoEmitter.cpp [TableGen] Improve the formatting of the emitted predicates (NFC) 2018-12-04 01:43:22 +00:00
IntrinsicEmitter.cpp Mark @llvm.trap cold 2018-11-14 19:53:41 +00:00
LLVMBuild.txt Add missing dependency (headers are included from MC, so a link dependency could exist easily enough) 2018-03-29 00:29:43 +00:00
OptParserEmitter.cpp
PredicateExpander.cpp [TableGen] Fix negation of simple predicates 2018-11-30 21:03:24 +00:00
PredicateExpander.h [tblgen][PredicateExpander] Add the ability to describe more complex constraints on instruction operands. 2018-10-31 12:28:05 +00:00
PseudoLoweringEmitter.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
RegisterBankEmitter.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
RegisterInfoEmitter.cpp Use the container form llvm::sort(C) 2018-10-31 00:31:06 +00:00
RISCVCompressInstEmitter.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
SDNodeProperties.cpp
SDNodeProperties.h
SearchableTableEmitter.cpp TableGen: Fix ASAN error 2018-10-31 17:46:21 +00:00
SequenceToOffsetTable.h
SubtargetEmitter.cpp [llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666). 2018-11-29 12:15:56 +00:00
SubtargetFeatureInfo.cpp IWYU for llvm-config.h in llvm, additions. 2018-04-30 14:59:11 +00:00
SubtargetFeatureInfo.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
TableGen.cpp [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel. 2018-10-25 07:44:01 +00:00
TableGenBackends.h [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel. 2018-10-25 07:44:01 +00:00
tdtags
Types.cpp
Types.h
WebAssemblyDisassemblerEmitter.cpp [WebAssembly] Read prefixed opcodes as ULEB128s 2018-11-09 01:57:00 +00:00
WebAssemblyDisassemblerEmitter.h [WebAssembly] Initial Disassembler. 2018-05-10 22:16:44 +00:00
X86DisassemblerShared.h
X86DisassemblerTables.cpp [X86] Remove DATA32_PREFIX. Hack the printing for DATA16_PREFIX to print 'data32' in 16-bit mode. Hack the asm parser to convert 'data32' to 'data16' in 16-bit mode. 2018-04-22 00:52:02 +00:00
X86DisassemblerTables.h
X86EVEX2VEXTablesEmitter.cpp [X86] Add the ability to force an EVEX2VEX mapping table entry from the .td files. Remove remaining manual table entries from the tablegen emitter. 2018-06-19 04:24:44 +00:00
X86FoldTablesEmitter.cpp [X86] More additions to the load folding tables based on the autogenerated tables. 2018-06-16 23:25:50 +00:00
X86ModRMFilters.cpp
X86ModRMFilters.h Test commit: remove trailing whitespace 2018-09-11 17:28:43 +00:00
X86RecognizableInstr.cpp [X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions. 2018-08-13 22:06:28 +00:00
X86RecognizableInstr.h [X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0. 2018-06-19 04:24:42 +00:00