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c7cbe2ad6b
Summary: Reported in https://github.com/opencv/opencv/issues/15413. We have serveral extended mnemonics for Move To/From Vector-Scalar Register Instructions eg: mffprd,mtfprd etc. We only support one of them, this patch add the others. Reviewers: nemanjai, steven.zhang, hfinkel, #powerpc Reviewed By: hfinkel Subscribers: wuzish, qcolombet, hiraditya, kbarton, MaskRay, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66963 llvm-svn: 370411
28 lines
800 B
LLVM
28 lines
800 B
LLVM
; RUN: llc -mcpu=generic -mtriple=powerpc64le-unknown-unknown -O0 < %s \
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; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=GENERIC
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; RUN: llc -mcpu=ppc -mtriple=powerpc64le-unknown-unknown -O0 < %s \
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; RUN: -verify-machineinstrs | FileCheck %s
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define i32 @bad(double %x) {
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%1 = fptoui double %x to i32
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ret i32 %1
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; CHECK: fctidz [[REG0:[0-9]+]], 1
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; CHECK: stfd [[REG0]], [[OFF:.*]](1)
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; CHECK: lwz {{[0-9]*}}, [[OFF]](1)
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; GENERIC: xscvdpuxws [[REG0:[0-9]+]], 1
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; GENERIC: mffprwz {{[0-9]*}}, [[REG0]]
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}
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define i32 @bad1(float %x) {
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entry:
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%0 = fptosi float %x to i32
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ret i32 %0
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; CHECK: fctiwz [[REG0:[0-9]+]], 1
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; CHECK: stfd [[REG0]], [[OFF:.*]](1)
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; CHECK: lwa {{[0-9]*}}, [[OFF]](1)
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; GENERIC: xscvdpsxws [[REG0:[0-9]+]], 1
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; GENERIC: mffprwz {{[0-9]*}}, [[REG0]]
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}
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